M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 141

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 117 of 587
11.6.3
The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority after the instruction in progress is completed. Then, the CPU starts the interrupt sequence from the
following cycle. However, for the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT, and RMPA
instructions, if an interrupt request is generated while one of these instructions is being executed, the MCU
suspends the instruction execution to start the interrupt sequence.
The interrupt sequence is performed as indicated below:
After the interrupt sequence is completed, the CPU executes the instruction from the starting address of the
interrupt routine.
NOTE:
(1) The CPU obtains the interrupt number by reading the address 000000h (address 000002h for the high-
(2) The FLG register value, immediately before the interrupt sequence, is saved to a temporary register
(3) Each bit in the FLG register becomes as follows:
(4) The internal register value (the FLG register value saved in (2)) in the CPU is saved to the stack; or to
(5) The PC value is saved to the stack; or to the SVP register for the high-speed interrupt.
(6) The interrupt priority level of the acknowledged interrupt becomes the IPL level.
(7) An interrupt vector corresponding to the acknowledged interrupt is stored into PC.
1. Temporary register cannot be accessed by users.
Interrupt Sequence
speed interrupt). Then, the corresponding IR bit to the interrupt becomes 0 (interrupt not requested).
the CPU.
the SVF register for the high-speed interrupt.
The I flag becomes 0 (interrupt disabled)
The D flag becomes 0 (single-step interrupt disabled)
The U flag becomes 0 (ISP selected)
11. Interrupts
(1)
in