M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 277

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 253 of 587
17.1.3.6 SDA Input
17.1.3.7 ACK, NACK
17.1.3.8 Transmit and Receive Operation Initialization
When the IICM2 bit in the UiSMR2 register (i = 0 to 4) is set to 0, the first eight bits of received data are stored
into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the
UiRB register. The eighth bit (D0) is stored into bit 8 in the UiRB register.
If the IICM2 bit is set to 1 and the CKPH bit in the UiSMR3 register is set to 1 (clock delay), the same data as
that of when setting the IICM2 bit to 0 can be returned, by reading the UiRB register after the rising edge of the
ninth bit of the serial clock.
When the STSPSEL bit in the UiSMR4 register is set to 0 (start/stop condition not output) and the ACKC bit in
the UiSMR4 register is set to 1 (ACK data output), the SDAi pin outputs the setting value, ACK or NACK, of
the ACKD bit in the UiSMR4 register.
If the IICM2 bit is set to 0, the NACK interrupt request is generated when the SDAi pin is held high (“H”) at the
rising edge of the ninth bit of the serial clock. The ACK interrupt request is generated when the SDAi pin is
held low (“L”) at the rising edge of the ninth bit of the serial clock.
When ACK is selected to generate a DMA request source, the DMA transfer is activated by an ACK detection.
The following occurs when the STC bit in the UiSMR2 register is set to 1 (UARTi initialized) and the start
condition is detected:
When UARTi transmit/receive operation is started with setting the STC bit to 1, the TI bit in the UiC1 register
remains unchanged. Also, select the external clock as the serial clock to start UARTi transmit/receive operation
with setting the STC bit to 1.
•
•
•
UARTi transmit shift register. Then, the transmit operation is started at the next serial clock input to the
SCLi pin. UARTi output value remains the same as when the start condition was detected until the first bit
data is output.
input to the SCLi pin.
from the SCLi pin becomes “L” at the falling edge of the ninth bit of the serial clock.
The UARTi transmit shift register is initialized and the contents of the UiTB register are transferred to the
The SWC bit in the UiSMR2 register becomes 1 (SCLi pin is held “L” after receiving 8th bit). An output
The UARTi receive shift register is initialized and the receive operation is started at the next serial clock
17. Serial Interfaces (UART0 to UART4)