M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 440

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 416 of 587
Figure 23.9
23.1.7
CANi Baud Rate Prescaler (i = 0, 1)
b7
The CiBRP register determines a Tq of the CAN bit time.
Number of Tq per bit = SS + PTS + PBS1 + PBS2
The CAN bit time is comprised of the following four segments.
Figure 23.10 shows a bit timing diagram.
NOTES:
(1) SS: Synchronization Segment
(2) PTS: Propagation Time Segment
(3) PBS1: Phase Buffer Segment 1
(4) PBS2: Phase Buffer Segment 2
•
1. Set the CiBRP register while the STATE_RESET bit in the CiSTR register is 1 (CAN module is in reset).
2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the
3. Do not set the CiBRP register to 00h (divide-by-1).
This is the amount of lengthening or shortening of the phase buffer segments to compensate for the phase
error.
SJW: Resynchronization Jump Width
clock to the CAN module.
CANi Baud Rate Prescaler (CiBRP Register) (i = 0, 1)
This segment is used to monitor the falling edge of a bit in order to synchronize the various CAN
modules.
This segment is used to compensate for the physical delay times within the CAN network. The physical
delay times within the network is twice the sum of the signal propagation delay on the CAN bus, the
input comparator delay, and the output driver delay.
This segment is used to compensate for the edge phase error caused by the frequency error. If the falling
edge of a bit comes in later than expected, PBS1 is lengthened by up to the resynchronization jump
width.
This segment has the same functionality to PBS1. If the falling edge of a bit comes in sooner than
expected, PBS2 is shortened by up to the resynchronization jump width.
Baud rate =
C0BRP and C1BRP Registers
Tq =
b0
If the setting value is n , the CAN clock is divided by n+1 .
CAN clock
Tq × number of Tq per bit
Symbol
C0BRP
C1BRP
BRP + 1
1
Function
(1)
Address
0217h
0297h
Tq: Time quantum
BRP: Setting value of the CiBRP register (1 to 255)
01h to FFh
Setting Range
(3)
After Reset
0000 0001b
0000 0001b
23. CAN Module
(2)
RW
RW