M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 258

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 234 of 587
17.1.2
Table 17.4
NOTES:
Data format
Baud rate
Transmit/receive control
Transmit start condition
Receive start condition
Interrupt request generation
timing
Error detection
Selectable function
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
Full-duplex asynchronous serial communications are allowed in this mode. Table 17.4 lists specifications of
UART mode. Table 17.5 lists pin settings. Figure 17.17 shows register settings. Figure 17.18 shows an example
of a transmit operation. Figure 17.19 shows an example of a receive operation.
register remains unchanged as 0 (interrupt not requested).
Clock Asynchronous (UART) Mode
Item
UART Mode Specifications
• Data length: selectable among 7 bits, 8 bits, or 9 bits long
• Start bit: 1 bit long
• Parity bit: selectable among odd, even, or none
• Stop bit: selectable from 1 bit or 2 bits long
fj / (16 (m + 1))
Selectable among CTS function, RTS function or CTS/RTS function disabled
To start transmit operation, all of the following must be met:
To start receive operation, all of the following must be met:
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
Receive interrupt:
• Overrun error
• Framing error
• Parity error
• Error sum flag
• LSB first or MSB first
• Serial data logic inverse
• TXD and RXD I/O polarity inverse
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Apply a low-level (“L”) signal to the CTSi pin when the CTS function is selected
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• The RI bit is 1 (no data in UiRB register) when RTS function is used.
• The start bit is detected
• The UiIRS bit is set to 0 (no data in the UiTB register):
• The UiIRS bit is set to 1 (transmit operation completed):
• When data is transferred from the UARTi receive shift register to the UiRB register
Overrun error occurs when the preceding bit of the final stop bit of the next data (the
first stop bit when selecting 2 stop bits) is received before reading the UiRB register
Framing error occurs when the number of the stop bits set by the STPS bit in the
UiMR register is not detected
Parity error occurs when parity is enabled and the received data does not have the
correct even or odd parity set by the PRY bit in the UiMR register.
Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs
Data is transmitted or received from either bit 0 or bit 7
Transmit and receive data are logically inverted. The start bit and stop bit are not
inverted
The level output from the TXD pin and the level applied to the RXD pin are inverted.
All the data including the start bit and stop bit are inverted.
fj = f1, f8, f2n
m: setting value of the UiBRG register (00h to FFh)
fEXT: clock input to the CLKi pin when the CKDIR bit in the UiMR register is
When the above two conditions are met, the RTSi pin output an “L” signal.
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
when the final stop bit is output from the UARTi transmit shift register
(receive operation completed)
set to 1 (external clock)
(2)
(1)
, fEXT
Specification
17. Serial Interfaces (UART0 to UART4)