M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 478

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 454 of 587
23.4.1
23.4.2
23.4.2.1
When a signal applied to the CAN1WU pin is at the falling edge, the CAN1WUR bit in the IIO5IR register
becomes 1 (interrupt requested), regardless of the value of the SLEEP bit in the C1SLPR register.
When P7_7 (CAN0IN) is used as a CAN0 input port, the CAN0 wake-up interrupt becomes available by using
event counter mode of TA3IN that shares a pin with CAN0.
When P8_3 (CAN0IN/CAN1IN) is used as a CAN input port, the CAN0 and CAN1 wake-up interrupts become
available by using INT1 that shares a pin with CAN0IN/CAN1IN.
The followings are the CANij interrupt request sources. (i = 0, 1; j = 0 to 2)
When the INTSEL bit in the CiCTLR1 register is set to 0, the result of logical sum of interrupt requests from the
above five sources becomes the CANij interrupt request.
When the INTSEL bit is set to 1, the interrupt requests from three types of CANij interrupt request sources,
which are CANi message slot k transmit operation completed, CANi message slot k receive operation
completed, and CANi error (bus error detected, error-passive state entered, and bus-off state entered), are
individually output.
When the INTSEL bit is set to 0 (output CAN interrupt request via OR gate), all the CANi0, CANi1, and
CANi2 interrupt requests are generated by any of the CANij interrupt source.
Table 23.5 lists interrupt sources and the corresponding interrupt registers (when INTSEL bit is set to 0). Figure
23.42 shows a CANij interrupt block diagram (when INTSEL bit is set to 0).
When a CANij interrupt request is generated, the interrupt status bit (the corresponding bit in the CiSISTR
register or CiEISTR register) becomes 1 (interrupt requested). And then, if the interrupt mask bit (the
corresponding bit in the CiSIMKR register or CiEIMKR register) is set to 1 (interrupt request enabled), all the
corresponding CANijR bits in the IIOnIR register (n = 9, 10, 11 when i = 0; n = 0, 1, 5 when i = 1) become 1
(interrupt requested).
NOTE:
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•
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1. The interrupt status bits in registers CiSISTR and CiEISTR are not cleared to 0 automatically when an
CANi message slot k (k = 0 to 15) transmit operation completed
CANi message slot k receive operation completed
CANi bus error detected
CANi error-passive state entered
CANi bus-off state entered
interrupt request is acknowledged. Set each bit to 0 by a program.
While any of enabled status bits remains 1, the CANijR bit does not become 1 (interrupt requested) when
a CANij interrupt request is generated.
CAN1 Wake-Up Interrupt
CANij Interrupt
When the INTSEL Bit is Set to 0
(output CAN interrupt request via OR gate)
23. CAN Module