M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 422

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 398 of 587
22.5.1
Table 22.25
NOTE:
Data format
Serial clock
Transmit start condition
Receive start condition
Interrupt request
generation timing
Error detection
Selectable function
1. The serial clock must be fBT2 divided by six or lower frequency when the internal clock is selected, and the
In variable data length clock synchronous mode, full-duplex clock synchronous serial communication is
allowed. Transmit data can be selected from 1 to 8 bits long. Continuous transmit/receive operations enable to
communicate more than 9 bit-long data. Table 22.25 lists specifications of the group 2 variable data length
clock synchronous mode. Table 22.26 lists register settings. Table 22.27 lists pin settings. Figure 22.61 shows
an example of a transmit and receive operation.
serial clock must be fBT2 divided by 20 or lower frequency when the external clock is selected. Additionally,
meet the conditions shown on Tables 27.26 and 27.49 Intelligent I/O communication function (Group 2) in
the chapter 27. Electrical Characteristics.
Variable Data Length Clock Synchronous Mode (Group 2)
Item
(1)
Variable Data Length Clock Synchronous Mode Specifications (Group 2)
Data length: variable
When the CKDIR bit in the G2MR register is set to 0 (internal clock):
When the CKDIR bit is set to 1 (external clock):
Transmit operation starts when all of the following conditions are met:
Receive operation starts when all of the following conditions are met:
Transmit interrupt (The IRS bit in the G2MR register selects one of the following):
Receive interrupt:
Overrun error
• LSB first or MSB first (Selectable only in 8-bits mode)
• ISTXD2 and ISRXD2 I/O polarity invert
The G2PO0 register determines a baud rate and the serial clock is generated in
phase-delayed waveform output mode of the channel 2.
The serial clock is input from the ISCLK2 pin.
• Set the TE bit in the G2CR register to 1 (transmit operation enabled)
• Data is written to the G2TB register
• Set the TE bit in the G2CR register to 1 (transmit operation enabled)
• Data is written to the G2TB register
• Set the RE bit in the G2CR register to 1 (receive operation enabled)
• The IRS bit is set to 0 (no data in the G2TB register):
• The IRS bit is set to 1 (transmit operation completed):
• When data is transferred from the receive shift register to the G2RB register (receive
When the transmit interrupt request is generated, the SIO2TR bit in the IIO6IR register
becomes 1 (interrupt requested) (See Figure 11.18).
When the receive interrupt request is generated, the SIO2RR bit in the IIO5IR register
becomes 1 (interrupt requested) (See Figure 11.18).
Overrun error occurs when the j
8)) is received before reading the G2RB register. If an overrun error occurs, a read
from the G2RB register returns an undefined value.
Data is transmitted and received from either bit 0 or bit 7.
Select LSB first except 8-bits mode.
ISTXD2 pin output level and ISRXD2 pin input level are inverted
When data is transferred from the G2TB register to the transmit shift register
(transmit operation started).
When data transmit operation from the transmit shift register is completed.
operation completed)
2(n + 2)
fBT2
n: setting value of the G2PO0 register
(0001h to FFFDh)
22. Intelligent I/O (Group 2 Communication Function)
th
stop bit of the next data (data length: j bits (j = 1 to
Specification