M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 49

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 25 of 587
2.2
2.3
Registers associated with the high-speed interrupt are as follows:
Refer to 11.4 High-Speed Interrupt for details.
Registers associated with the DMAC are as follows:
Refer to 13. DMAC for details.
2.1.8.7
2.1.8.8
2.1.8.9
2.1.8.10 Reserved Space
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Flag save register (SVF)
PC save register (SVP)
Vector register (VCT)
DMA mode register (DMD0, DMD1)
DMA transfer count register (DCT0, DCT1)
DMA transfer count reload register (DRC0, DRC1)
DMA memory address register (DMA0, DMA1)
DMA memory address reload register (DRA0, DRA1)
DMA SFR address register (DSA0, DSA1)
High-Speed Interrupt Registers
DMAC-Associated Registers
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when
an interrupt request is acknowledged.
ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1.
The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying
software interrupt numbers 0 to 31 is executed.
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority level than IPL, the interrupt is enabled.
Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.
Interrupt Enable Flag (I)
Stack Pointer Select Flag (U)
Processor Interrupt Priority Level (IPL)
2. Central Processing Unit (CPU)