M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 430

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 406 of 587
23.1.1.1 RESET1 and RESET0 Bits
23.1.1.2 LOOPBACK Bit
23.1.1.3 BASICCAN Bit
When both the RESET1 and RESET0 bits are set to 1 (CAN module is reset), the CAN module is immediately
reset regardless of ongoing CAN communication.
After both the RESET1 and RESET0 bits are set to 1 and the CAN module reset is completed, the CiTSR
register (i = 0, 1) becomes 0000h. Also, registers CiTEC and CiREC become 00h and both the
STATE_ERRPAS and STATE_BUSOFF bits in the CiSTR register become 0.
When both the RESET1 and RESET0 bits are changed from 1 to 0, the CiTSR register starts counting and the
CAN module is permitted to communicate after 11 consecutive recessive bits have been detected.
NOTES:
When the LOOPBACK bit is set to 1 (loopback function enabled) and the receive message slot has the
identifier (ID) and frame format matched with a transmitted frame, the transmitted frame is stored to the receive
message slot.
NOTES:
When the BASICCAN bit is set to 1, the message slots 14 and 15 enter BasicCAN mode.
In BasicCAN mode, the message slots 14 and 15 are configured as double buffered.
Acceptance filtering permits the receive frames having the matching IDs to be stored into the message slots 14
and 15 alternately. Both data frame and remote frame can be received.
Use the following procedure to enter BasicCAN mode.
(1) Set the BASICCAN bit to 1.
(2) Set the same ID to the message slots 14 and 15.
(3) Set the same values in registers CiLMAR0 to CiLMAR4 and CiLMBR0 to CiLMBR4.
(4) Set the same value to bits IDE14 and IDE15 in the CiIDR register.
(5) Set registers CiMCTL14 and CiMCTL15 to receive a data frame.
NOTES:
1. Set the same value to both the RESET1 and RESET0 bits simultaneously.
2. Ensure that the STATE_RESET bit in the CiSTR register becomes 1 (CAN module is in reset) after both
3. The CANiOUT pin outputs a high-level (“H”) signal as soon as both the RESET1 and RESET0 bits are set
4. To select pins CANiIN and CANiOUT for CAN communication, set registers PS1, PS2, PS3, PSL1,
1. No ACK for the transmitted frame is returned.
2. Change the LOOPBACK bit setting while the STATE_RESET bit is 1 (CAN module is in
1. Change the BASICCAN bit setting while the STATE_RESET bit is 1 (CAN module is in reset).
2. The message slot 14 is the first slot to become active after both the RESET1 and RESET0 bits are set to 0.
3. The message slots 0 to 13 are not affected by entering BasicCAN mode.
reset).
the RESET1 and RESET0 bits are set to 1.
to 1. CAN bus error may occur by setting both the RESET1 and RESET0 bits to 1 while the CAN frame is
being transmitted.
PSL2, PSL3, PSC, PSC2, PSC3, IPS, IPSA, PD7, PD8, and PD9 while the STATE_RESET bit is 1 (CAN
module is in reset).
23. CAN Module