M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 126

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 102 of 587
Figure 9.15
(1) Initial setting
(2) Before entering stop mode
(3) After exiting wait mode
NOTE:
RLVL register: bits RLVL2 to RLVL0 = 7
I flag = 0
FLG register: set IPL
Bits RLVL2 to RLVL0 = the same level as IPL
PRCR register: PRC0 bit = 1
CM1 register: CM17 bit = 0
CM2 register: CM21 bit = 0
CM0 register: CM07 bit = 0
PM2 register: PM24 bit = 0
I flag = 1
CM1 register: CM10 bit = 1
RLVL register: bits RLVL2 to RLVL0 = 7
1. Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1.
Set the interrupt priority level (ILVL2 to ILVL0) of
LABEL_001:
CM2 register: CM20 bit = 0
Set the interrupt priority level of the interrupts,
Set an interrupt priority level of each interrupt
When the oscillation stop detect function is used
which is not used to exit stop mode, to 0
bset 0,
jmp.b LABEL_001 ; jmp.b instruction executed (no instruction
nop
nop
nop
nop
mov.b #0, prcr
the interrupt used to exit stop mode
Procedure to Enter Stop Mode
PRC1 bit = 1
cm1
.
.
.
Stop mode
Start
End
; between jmp.b and LABEL.)
; all clocks stopped (stop mode)
; nop(1)
; nop(2)
; nop(3)
; nop(4)
; protection set
(Note 1)
Set the wait/stop mode
exit interrupt priority level to 7.
Interrupt disabled
(ILVL2 to ILVL0)
Set the processor interrupt priority level (IPL)*
Set the exit interrupt priority level (RLVL2 to RLVL0)*
Enable writing to registers associated with clocks
Select the main clock as the CPU clock source
(Set after a main clock oscillation stabilizes)
Disable oscillation stop detect function
Interrupt enabled
All clocks stop
Set the exit priority level as soon as exiting wait mode
> IPL* = (RLVL2 to RLVL0)*
9. Clock Generation Circuits