M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 346

IC M32C/87 MCU FLASH 144LQFP

M3087BFLBGP#U5

Manufacturer Part Number
M3087BFLBGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M3087BFLBGP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 322 of 587
Figure 22.1
Overflow of bit 15 in the base timer
BTRE: Bit in the G1POCR0 register
BT1S: Bit in the BTSR register
BCK1 and BCK0, DIV4 to DIV0: Bits in the G1BCR0 register
BTS: Bit in the G1BCR1 register
CTS1 and CTS0, DF1 and DF0, GT, PR: Bits in the G1TMCRj register (j = 0 to 7)
MOD2 to MOD0: Bits in the G1POCRj register
NOTE:
ISRXD1 /
INPC1_0
INPC1_1
INPC1_2
INPC1_3
INPC1_4
INPC1_5
INPC1_6
INPC1_7
Overflow of bit 9 in the base timer
ISCLK1 /
1. After a clock, which is selected in the G1BCR0 register, is supplied to the registers, each register value becomes the after reset value.
Two phase
pulse input
BT1S
BTS
Request from INT pin
BCK1 and BCK0
f1
Time Measurement/Waveform Generation Function in Group 1 Block Diagram
11
10
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
filter
filter
filter
filter
filter
filter
filter
filter
DF1 and DF0
00
00
00
00
00
00
00
00
10: fBT1
11: f1
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
10, 11
function
function
Gate
Gate
DIV4 to DIV0
Reset
0
1
Divider
2(n+1)
BTRE
CTS1 and CTS0
Select
Select
Select
Select
Select
Select
Select
Select
0
1
0
1
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Clock input to ISCLK1 pin
Receive data input to ISRXD1 pin
GT
GT
Reset signal by matching the base
timer with the G1PO0 register
fBT1
Prescaler
Prescaler
function
function
Base timer reset
G1TM0, G1PO0
G1TM1, G1PO1
G1TM2, G1PO2
G1TM3, G1PO3
G1TM4, G1PO4
G1TM6, G1PO6
G1TM7, G1PO7
G1TM5, G1PO5
Base timer
registers
registers
registers
registers
registers
registers
registers
registers
0
1
0
1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PR
PR
communication
signal from the
Transmit data
function
output
output
output
PWM
PWM
PWM
output
PWM
000 to 010
111
000 to 010
111
MOD2 to MOD0
OUTC1_4
OUTC1_5
OUTC1_6
OUTC1_7
Ch0 to ch7
interrupt request signal
MOD2 to MOD0
OUTC1_0 / ISTXD1
Ch1 generation clock
OUTC1_1 / ISCLK1
Clock synchorous mode
serial clock
OUTC1_2
ch2 generation clock
OUTC1_3
ch3 generation clock
22. Intelligent I/O

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