M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 589

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 565 of 587
28.7
28.7.1
28.7.2
28.7.3
After reset, ISP is initialized to 000000h. The program may go out of control if an interrupt is acknowledged
before setting a value to ISP. Therefore, ISP must be set before any interrupt request is acknowledged. Setting
ISP to an even address allows interrupt sequences to be executed at a higher speed.
To use the NMI interrupt, set ISP at the very beginning of the program. The NMI interrupt can be
acknowledged after the first instruction has been executed after reset.
Interrupts
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•
•
•
•
Figure 28.3 shows a procedure to set the INTi interrupt source (i = 0 to 5).
The NMI interrupt cannot be disabled. Connect the NMI pin to VCC1 via a resistor (pull-up) when not in
use.
The P8_5 bit in the P8 register indicates the voltage level applied to the NMI pin. Read the P8_5 bit only to
determine the pin level after the NMI interrupt occurs.
Edge Sensitive
Level Sensitive
The IR bit in the INTiIC register (i = 0 to 5) may become 1 (interrupt requested) when the polarity settings
of pins INT0 to INT5 are changed. Set the IR bit to 0 (interrupt not requested) after the polarity setting is
changed.
Each “H” or “L” width of the signal applied to pins INT0 to INT8 must be 250 ns or more regardless of
the CPU clock frequency.
Each “H” or “L” width of the signal applied to pins INT0 to INT5 must be one CPU clock cycle + 200 ns
or more. For example, each “H” or “L” width must be 234 ns or more if the CPU clock is 30 MHz.
ISP Setting
NMI Interrupt
INT Interrupt
28. Usage Notes