M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 188

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 164 of 587
Figure 15.6
Timer Ai Mode Register (i = 0 to 4)(Event Counter Mode)
b7
b6 b5 b4
NOTES:
0
1. Bits TAiTGH and TAiTGL in the ONSF or TRGSR register determine a count source in event counter mode.
2. The MR1 bit is enabled only when counting external signals.
3. The counter decrements when an “L” signal is applied to the TAiOUT pin. The counter increments when an “H” signal is applied
4. The TCK1 bit is enabled only in the TA3MR register. The TCK1 bit in registers TA0MR to TA2MR and TA4MR are disabled.
5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j = 2 to 4) to 1 (two-phase pulse signal processing
to the TAiOUT pin.
function enabled). Also, set bits TAjTGH and TAjTGL in the TRGSR register to 00b (input to the TAjIN pin).
b3
b2
TA0MR to TA4MR Registers in Event Counter Mode
0
b1
0
b0
1
Bit Symbol
TMOD0
TMOD1
TCK0
TCK1
MR1
MR2
MR3
Symbol
(b2)
TA0MR to TA4MR
−
Operating mode select bits
Reserved bit
Count polarity select bit
Increment/decrement
switching source select bit
Set to 0 in event counter mode
Count operation type
select bit
Two-phase pulse signal
processing operation
select bit
(4,5)
Bit Name
Address
0356h, 0357h, 0358h, 0359h, 035Ah
(2)
b1 b0
0 1: Event counter mode
Set to 0
0: UDF registser setting
1: Signal applied to the
0: Reload
1: Free running
Set to 0
0: Falling edges of an
1: Rising edges of an
two-phase pulse signals)
external signal counted
external signal counted
TAiOUT pin
(When not processing
Function
(3)
(1)
Set to 0
Set to 1
0: Normal processing
1: Multiply-by-4
two-phase pulse signals)
operation
processing operation
(When processing
Function
After Reset
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
15. Timer A