M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 179

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 155 of 587
14.2
14.3
14.1.3
14.1.4
14.1.5
14.3.1
The DMACII function is selected by setting the DMAII bit to 1 (interrupt priority level 7 is used for DMACII
transfer). DMACII transfer request is generated by interrupt requests from any peripheral function with bits ILVL2
to ILVL0 set to 111b (level 7). These peripheral function interrupt requests are used as DMACII transfer requests
and the peripheral function interrupts cannot be used.
When an interrupt request with bits ILVL2 to ILVL0 set to 111b (level 7) is generated, DMACII is activated
regardless of the I flag and IPL settings.
DMACII transfers data in 8-bit units or 16-bit units.
When a 16-bit data is transferred to a destination address 0FFFFh, it is transferred to addresses 0FFFFh and
10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is transferred
to a given destination address.
The actual transferable space varies depending on internal RAM capacity. Refer to Figure 3.1 for the internal
memory.
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To use the peripheral function interrupt as a DMACII request source, set bits ILVL2 to ILVL0 to 111b (level 7).
Set the starting address of the DMACII index in an interrupt vector for the peripheral function interrupt used as
a DMACII request source. When using the chain transfer, the relocatable vector table must be located in the
RAM.
When the intelligent I/O interrupt, CAN interrupt, INTj interrupt (j = 6 to 8), UARTk (k = 5, 6) transmit
interrupt, or UARTk receive interrupt is used to activate DMACII, set the IRLT bit in the corresponding IIOiIE
register (i = 0 to 11) to 0 (interrupt request is used for DMAC, DMACII).
Data transfer between any two memory locations in the 64-Kbyte space can be:
When an incremented address is selected, DMACII increments an address after every transfer for the following
transfer. In a 8-bit data transfer, a transfer address is incremented by one. In a 16-bit data transfer, a transfer
address is incremented by two.
When a source or destination address exceeds 0FFFFh as a result of address incrementation, the source or
destination address returns to 00000h and continues incrementation. Maintain source and destination address at
0FFFFh or below.
Memory-to-memory transfer: data is transferred from a given memory location in the 64-Kbyte space
(addresses 00000h to 0FFFFh) to another given memory location in the same space.
Immediate data transfer: immediate data is transferred to a given memory location in the 64-Kbyte space.
Calculation transfer: two 8-bit or two 16-bit data are added together and the result is transferred to a given
memory location in the 64-Kbyte space.
DMACII Performance
Transfer Data
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a transfer from a fixed address to another fixed address;
a transfer from a fixed address to an incremented address;
a transfer from an incremented address to a fixed address;
a transfer from an incremented address to another incremented address.
Interrupt Control Register for the Peripheral Function
Relocatable Vector Table for the Peripheral Function
IRLT Bit in the IIOiIE Register (i = 0 to 11)
Memory-to-memory Transfer
14. DMACII