M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 528

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 504 of 587
26.3.2
Table 26.4
SRD: Data in the status register (D7 to D0)
WA: Write address (The address specified in the first bus cycle is the same even address
WD: 16-bit write data
BA: Highest-order even address of a block
x: Any even address in the user ROM area
xx: 8 high-order bits of command code (ignored)
26.3.2.1
Read array
Read status register
Clear status register
Program
Block erase
Lock bit program
Read lock bit status
26.3.2.2
26.3.2.3
as the write address specified in the second bus cycle.)
Read or write commands and data from or to even addresses in the user ROM area in 16-bit units.
When writing a command code, 8 high-order bits (D15 to D8) are ignored.
The read array command is used to read the flash memory.
The flash memory enters read array mode when the command code xxFFh is written in the first bus cycle. The
content of the specified address can be read in 16-bit units when a read address is specified after the next bus
cycle. The flash memory remains in read array mode until the other command is written. Therefore, the contents
of multiple addresses can be read in succession.
The read status register command is used to read the status register. When the command code xx70h is written
in the first bus cycle, the status register can be read after the second bus cycle (refer to 26.3.4 Status Register
(SRD Register) for details). To read the status register, read an even address in the user ROM area. Do not
execute this command in EW1 mode.
The clear status register command is used to clear the status register. When the command code xx50h is written
in the first bus cycle, bits FMR07 and FMR06 in the FMR0 register become 00b and bits SR5 and SR4 in the
status register become 00b.
Software Command
Software Commands
Software Commands
Read Array Command
Read Status Register Command
Clear Status Register Command
Mode
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Address
WA
BA
x
x
x
x
x
(D15 to D0)
xxFFh
xx70h
xx50h
xx40h
xx77h
xx71h
xx20h
Data
Mode
Read
Write
Write
Write
Write
−
−
Second Bus Cycle
Address
WA
BA
BA
BA
−
−
x
26. Flash Memory
(D15 to D0)
xxD0h
xxD0h
xxD0h
Data
SRD
WD
−
−