M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 364

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 340 of 587
Figure 22.17
(3) When the RST1 bit in the G1BCR1 register is set to 1
(1) When the IT bit in the G1BCR0 register is set to 0 (base timer interrupt request occurs when bit 15 is changed from 1 to 0)
(2) When the IT bit in the G1BCR0 register is set to 1 (base timer interrupt request occurs when bit 14 is changed from 1 to 0)
(Base timer is reset by matching the base timer and the G1PO0 register)
The above applies under the following conditions:
- G1BCR1 register: the RST1 bit is set to 0 (Base timer is not reset by matching the base timer and the G1PO0 register)
The above applies under the following conditions:
- G1BCR1 register: the RST1 bit is set to 0 (Base timer is not reset by matching the base timer and the G1PO0 register)
The above applies under the following conditions:
- The G1PO0 register is set to 8000h
- Bits UD1 and UD0 in the G1BCR1 register are set to 01b (counter increment/decrement mode)
Contents of the
Contents of the
Contents of the
Status of bit 15
BT1R bit in the
Status of bit 14
BT1R bit in the
IIO4IR register
IIO4IR register
Base Timer Operation in Count Increment/Decrement Mode (Group 1)
counter
counter
counter
bits UD1 and UD0 are set to 01b (counter increment/decrement mode)
bits UD1 and UD0 are set to 01b (counter increment/decrement mode)
FFFFh
FFFFh
C000h
8000h
0000h
8000h
4000h
0000h
8002h
8000h
0000h
1
0
1
0
1
0
1
0
Set to 0 by a program
Set to 0 by a program
22. Intelligent I/O (Base Timer)