M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 479

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 455 of 587
Figure 23.42
Table 23.5
CANi message slot 0
receive operation
completed
CANi message slot 0
transmit operation
completed
CANi message slot 15
receive operation
completed
CANi message slot 15
transmit operation
completed
CANij interrupt source
CANi message slot k
receive operation
completed
CANi message slot k
transmit operation
completed
CANi bus error detected
CANi error-passive state
entered
CANi bus-off state
entered
CANi bus error
detected
CANi error-passive
state entered
CANi bus-off state
entered
i = 0, 1
Interrupt Sources and Interrupt Registers (When INTSEL Bit is Set to 0)
CANij Interrupt Block Diagram (When INTSEL Bit is Set to 0)
CANi Interrupt
Interrupt status bit
0: interrupt not
1: interrupt requested
SISk bit in the
CiSISTR register
BEIS bit in the
CiEISTR register
EPIS bit in the
CiEISTR register
BOIS bit in the
CiEISTR register
requested
SIM15 bit
SIS15 bit
BOIM bit
BEIM bit
EPIM bit
BOIS bit
SIM0 bit
BEIS bit
EPIS bit
SIS0 bit
CANij Interrupt
Interrupt mask bit
0: interrupt request
1: interrupt request
SIMk bit in the
CiSIMKR register
BEIM bit in the
CiEIMKR register
EPIM bit in the
CiEIMKR register
BOIM bit in the
CiEIMKR register
disabled
enabled
1
1
1
0
0
0
INTSEL bit
INTSEL bit
INTSEL bit
Intelligent I/O interrupt
request
0: interrupt not requested
1: interrupt requested
When i = 0,
CAN0jR bit in registers
IIO9IR, IIO10IR, and
IIO11IR
When i = 1,
CAN1jR bit in registers
IIO0IR, IIO1IR, and
IIO5IR
Intelligent I/O interrupt
Intelligent I/O
CANi0R bit
CANi1R bit
CANi2R bit
interrupt
23. CAN Module