M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 144

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 120 of 587
Figure 11.9
11.6.7
11.6.8
11.6.9
When the REIT instruction is executed at the end of an interrupt routine, the values of the FLG register and PC,
which have been saved to the stack before the interrupt sequence is performed, are automatically restored. And
then, the program that was running before an interrupt request was acknowledged, resumes its process. The
high-speed interrupt uses the FREIT instruction instead. Refer to 11.4 High-Speed Interrupt for details.
Before executing the REIT or FREIT instruction, use the POPM instruction or the like to restore registers saved
by a program in the interrupt routine. By executing the REIT or FREIT instruction, register bank is switched
back to the bank used immediately before the interrupt sequence.
If two or more interrupt requests are detected at the same sampling points (a timing to check whether any
interrupt request is generated or not), the interrupt with the highest priority is acknowledged.
Set bits ILVL2 to ILVL0 in the Interrupt Control Register to select the given priority level for maskable
interrupts (peripheral function interrupts).
Priority levels of special interrupts, such as NMI and watchdog timer interrupt are fixed by hardware. Figure
11.9 shows the priority of hardware interrupts.
The interrupt priority does not affect software interrupts. Executing an instruction for a software interrupt
causes the MCU to execute an interrupt routine.
The interrupt priority level decision circuit selects the highest priority interrupt when two or more interrupt
requests are generated at the same sampling point.
Figure 11.10 shows the interrupt priority level decision circuit.
Returning from Interrupt Routine
Interrupt Priority
Interrupt Priority Level Decision Circuit
Interrupt Priority of Hardware Interrupts
Oscillation stop detection
Peripheral function
Watchdog timer
Vdet4 detection
Address match
NMI
H
L
11. Interrupts