M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 249

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 225 of 587
17.1.1
Table 17.2
NOTES:
Data format
Serial clock
Baud rate
Transmit/receive control
Transmit and receive
start condition
Interrupt request
generation timing
Error detection
Selectable function
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the
3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
Full-duplex clock synchronous serial communications are allowed in this mode. CTS/RTS function can be used
for transmit and receive control.
Table 17.2 lists specifications of clock synchronous mode. Table 17.3 lists pin settings. Figure 17.11 shows
register settings. Figure 17.12 shows an example of a transmit and receive operation when an internal clock is
selected. Figure 17.13 shows an example of a receive operation when an external clock is selected.
UiC0 register is set to 0, and that an “L” signal is applied when the CKPOL bit is set to 1.
register remains unchanged as 0 (interrupt not requested).
Clock Synchronous Mode
Item
Clock Synchronous Mode Specifications
Data length: 8 bits long
Internal clock or external clock can be selected by the CKDIR bit in the UiMR register
(i = 0 to 4)
• When the CKDIR bit is set to 0 (internal clock):
• When the CKDIR bit is set to 1 (external clock): clock input to the CLKi pin
Selectable among the CTS function, RTS function, or CTS/RTS function disabled
Internal clock is selected:
External clock is selected
If transmit-only operation is performed, the RE bit setting is not required in both cases.
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
Receive interrupt:
• Overrun error
• CLK polarity
• LSB first or MSB first
• Serial data logic inverse
• Continuous receive mode
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• “L” signal is applied to the CTSi pin when the CTS function is used
• Set the TE bit to 1
• The TI bit is 0
• Set the RE bit to 1
• The RI bit in the UiC1 register is 0 when the RTS function is used
• The UiIRS bit is set to 0 (no data in the UiTB register):
• The UiIRS bit is set to 1 (transmit operation completed):
• When data is transferred from the UARTi receive shift register to the UiRB register
Overrun error occurs when the 7th bit of the next data is received before reading the
UiRB register
Transmit data output timing and receive data input timing can be selected
Data is transmitted and received from either bit 0 or bit 7
Transmit and receive data are logically inverted
The TI bit becomes 0 by reading the UiRB register
fj / (2 (m + 1)
fj = f1, f8, f2n
(transmit operation started)
When above 4 conditions are met, RTSi pin outputs “L”
when data is transferred from the UiTB register to the UARTi transmit shift register
when data transmit operation from the UARTi transmit shift register is completed
(receive operation completed)
(3)
(1)
m: setting value of the UiBRG register (00h to FFh)
(2)
:
Specification
17. Serial Interfaces (UART0 to UART4)