M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 132

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 108 of 587
11.3
11.3.1
11.3.2
11.3.3
Special interrupts and peripheral function interrupts are available as hardware interrupts.
11.3.1.1
11.3.1.2
11.3.1.3
11.3.1.4
11.3.1.5
11.3.1.6
Special interrupts are non-maskable.
The NMI interrupt occurs when a signal applied to the NMI pin changes from high level (“H”) to low level
(“L”). Refer to 11.8 NMI Interrupt for details.
The watchdog timer interrupt occurs when the watchdog timer counter underflows. Refer to 12. Watchdog
Timer for details.
The oscillation stop detection interrupt occurs when the MCU detects a loss of the main clock. Refer to 9.
Clock Generation Circuits for details.
The Vdet4 detection interrupt occurs when the voltage applied to VCC1 rises above or drops below Vdet4.
Refer to 6.2 Vdet4 Detection Function for details.
Do not use the single-step interrupt. This is for use with development support tool only.
When the AIERi bit in the AIER register is set to 1 (address match interrupt enabled), the address match
interrupt occurs immediately before executing the instruction stored in the address indicated by the RMADi
register (i = 0 to 7).
Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if
a table data or any address other than the starting address of the instruction is set. Refer to 11.10 Address
Match Interrupt for details.
The DMACII transfer complete interrupt is generated by the DMACII function. Refer to 14. DMACII for
details.
The peripheral function interrupt is generated by the on-chip peripheral functions. The peripheral function
interrupts and software interrupt numbers 8 to 54 and 57 for the INT instruction use the same interrupt vector
table. The peripheral function interrupt is maskable.
See Tables 11.2 and 11.3 for the peripheral function interrupt sources. Refer to the descriptions of individual
peripheral functions for details.
Hardware Interrupts
Special Interrupts
DMACII End-of-Transfer Complete Interrupt
Peripheral Function Interrupt
NMI Interrupt
Watchdog Timer Interrupt
Oscillation Stop Detection Interrupt
Vdet4 Detection Interrupt
Single-Step Interrupt
Address Match Interrupt
11. Interrupts