M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 266

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 242 of 587
17.1.3
Table 17.7
NOTES:
Data format
Baud rate
Transmit start condition
Receive start condition
Interrupt request generation
timing
Error detection
Selectable function
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, satisfy the conditions while an “H” signal is applied to the SCLi pin.
3. If an overrun error occurs, a read from the UiRB register returns undefined values.
In I
Table 17.7 lists specifications of I
list individual functions in I
mode. Figure 17.24 shows a transfer timing to the UiRB register (i = 0 to 4) and interrupt timing.
2
C mode, the simplified I
Special Mode 1 (I
Item
I
2
C Mode Specifications
• Data length: 8 bits long
• In master mode
• In slave mode
To start transmit operation, all of the following must be met
To start receive operation, all of the following must be met
• Start condition detection
• Stop condition detection
• ACK (Acknowledge) detection
• NACK (Not-Acknowledge) detection
• Overrun error
• Arbitration lost detect timing
• SDAi digital delay
• Clock phase setting
When the CKDIR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock):
When the CKDIR bit is set to 1 (external clock): input from the SCLi pin
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Set the TE bit to 1 (transmit operation enabled)
• The TI bit is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
Overrun error occurs when the 8th bit of the next data is received before reading the
UiRB register
Update timing of the ABT bit in the UiRB register (i = 0 to 4) can be selected.
No digital delay or 2 to 8 cycle delay of the UiBRG count source can be selected.
Clock delay or no clock delay can be selected.
2
2
C mode. Table 17.12 lists pin settings. Figure 17.23 shows a block diagram of I
fj = f1, f8, f2n
fj / (2 (m + 1))
C helps to communicate with external devices.
2
C Mode)
2
C mode. Tables 17.8 and 17.9 list register settings. Tables 17.10 and 17.11
(3)
(1)
m: setting value of the UiBRG register (00h to FFh)
Specification
17. Serial Interfaces (UART0 to UART4)
(2)
(2)
:
:
2
C