M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 590
![IC M32C/87 MCU FLASH 144LQFP](/photos/12/31/123104/m3087bflbgp_u5_sml.jpg)
M3087BFLBGP#U5
Manufacturer Part Number
M3087BFLBGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M3087BFLGPU3.pdf
(629 pages)
Specifications of M3087BFLBGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M3087BFLBGP#U5M3087BFLBGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 590 of 629
- Download datasheet (16Mb)
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 566 of 587
Figure 28.3
< Procedure for Edge Sensitive >
< Procedure for Level Sensitive >
INTiIC register: bits ILVL2 to ILVL0 = 000b
IFSR register: IFSRi bit
INTiIC register: POL bit
INTiIC register: IR bit = 0
INTiIC register: bits ILVL2 to ILVL0
INTiIC register: bits ILVL2 to ILVL0 = 000b
IFSR register: IFSRi bit = 0
INTiIC register: POL bit
INTiIC register: IR bit = 0
INTiIC register: bits ILVL2 to ILVL0
Procedure to set the INTi Interrupt Source (i = 0 to 5)
LVS bit = 0
LVS bit = 1
Start
Start
End
End
Interrupt disabled
Select either one edge or both edges
Select polarity (Set to 0 when both edges are selected)
Select edge sensitive
Clear the interrupt request bit
Interrupt enabled
Interrupt disabled
Select one edge
Select polarity
Select level sensitive
Clear the interrupt request bit
Interrupt enabled
i = 0 to 5
28. Usage Notes
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