M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 296

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 272 of 587
17.2
Figure 17.40
RXDi
CTSi / RTSi
Figure 17.40 shows a UART5 and UART6 block diagram. Figures 17.41 to 17.45 show the registers associated
with UART5 and UART6. Refer to the tables listing register and pin settings in each mode. Refer to 11.11
Intelligent I/O, CAN, UART5, UART6, and INT6 to INT8 Interrupts for details on UART5 and UART6
transmit/receive interrupts.
F2n
SP
m: Setting value of the UiBRG register
NOTES:
i = 5, 6
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, CKDIR: bits in the UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: bits in the UiC0 register
(1)
f1
f8
RXDi
CLK1 and CLK0
CLKi
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Select either I/O port (CLKi input) or CLKi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports .)
3. Select either I/O port or RTSi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports .)
UART5 and UART6
00
01
10
SP
SP
1
0
Function Select
Register
Function Select
Register
UART5 and UART6 Block Diagram
STPS
CKDIR
0
1
0
1
STPS
0
CLKi output
CLKi input
(2)
(3)
SP
0
RTSi output
CTSi input
SMD2 to SMD0
1/(m+1)
register
SMD2 to SMD0
UiBRG
PAR
0
PAR
switching
switching
CKPOL
0
Polarity
Polarity
0
1
PRYE
CRD
CRS
0
1
PRYE
0
001
100
101
110
100
101
110
001
0
0
1/16
1/16
1/2
D8
D8
b8
b8
High-order bits of data bus
Low-order bits of data bus
110
110
001
101
001
101
100, 101, 110
100, 101, 110
0
1
CKDIR
b7
b7
001
001
SMD2 to SMD0
001
101
110
001
101
110
100
100
Logic inverse circuit + MSB/LSB conversion circuit
Logic inverse circuit + MSB/LSB conversion circuit
D7
D7
D6
D6
b6
b6
control circuit
17. Serial Interfaces (UART5 and UART6)
control unit
Transmit
Receive
UARTi transmit shift register
UARTi receive shift register
D5
D5
b5
b5
D4
D4
b4
b4
D3
D3
b3
b3
Receive
clock
Transmit
clock
b2
D2
D2
b2
D1
D1
b1
b1
Transmit/
receive
unit
D0
D0
b0
b0
UiTB register
UiRB register
TXDi
TXDi