M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 592

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 568 of 587
28.8
• Set the DMAC-associated registers while bits MDi1 and MDi0 (i = 0 to 3) in the channel i are set to 00b (DMA
• Write a 1 (requested) to the DRQ bit when setting the DMiSL register.
• To start a DMA transfer using a software trigger, set bits DSR and DRQ in the DMiSL register to 1
• While the DCTi register in the channel i is set to 1, do not generate a DMA request in the channel i in the timing
• Select a peripheral function used as a DMA request source after setting the DMA-associated registers. When the
• Wait six CPU clock cycles or more by a program to enable DMA after setting the DMiSL register
In the M32C/80 Series, if a DMA request is generated but a receiving channel is not ready
not occur and the DRQ bit becomes 0.
disabled). Then, set bits MDi1 and MDi0 to 01b (single transfer) or 11b (repeat transfer) at the end of the setup
procedure, which enables the DMA request of the channel i to be acknowledged.
simultaneously.
that bits MDi1 and MDi0 in the DMDj register (j = 0, 1) corresponding to the channel i are set to 01b (single
transfer) or 11b (repeat transfer). (Technical update: TN-M16C-88-0209)
INT interrupt is selected as a DMA request source, do not set the DCTi register to 1.
NOTE:
NOTE:
e.g.,
DMAC
1. Bits MDi1 and MDi0 are set to 00b or the DCTi register is 0000h (transferred 0 time).
2. To enable DMA means changing bits MDi1 and MDi0 in the DMDj register from 00b (DMA disabled)
OR.B #0A0h, DMiSL
to 01b (single transfer) or 11b (repeat transfer).
; set bits DSR and DRQ to 1 simultaneously
(1)
, a DMA transfer does
(2)
28. Usage Notes
.