M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 271

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 247 of 587
Table 17.11
NOTES:
i = 0 to 4
Reading RXDi, SCLi pin
levels
Default value of TXDi,
SDAi output
SCLi default and end
values
DMA source
(See Figure 17.24)
Storing receive data
Reading receive data
1. Set default value of the SDAi output while bits SMD2 to SMD0 in the UiMR register are set to 000b (serial
2. Second data transfer to the UiRB register (at the rising edge of the ninth bit of SCLi).
3. First data transfer to the UiRB register (at the falling edge of the ninth bit of SCLi).
interface disabled).
Function
Functions in I
Can be read regardless of the corresponding port direction bit
Value set in the port register before entering I
H
Acknowledgement detection (ACKi)
1st to 8th bit of the receive data are stored
into bits 7 to 0 in the UiRB register
The value in the UiRB register is read as it is
(no clock delay)
CKPH = 0
2
C Mode (2/2)
(NACK/ACK interrupt)
IICM2 = 0
I
L
2
C Mode (SMD2 to SMD0 = 010b, IICM = 1)
(clock delay)
CKPH = 1
H
UARTi receive operation - at the falling edge
of 9th bit of SCLi
1st to 7th bits of the receive data are stored
into bits 6 to 0 in the UiRB register. 8th bit is
stored into bit 8 in the UiRB register
2
C mode
(no clock delay)
17. Serial Interfaces (UART0 to UART4)
(UART transmit/receive interrupt)
CKPH = 0
(1)
IICM2 = 1
L
1st to 8th bits are
stored into bits 7 to 0
in the UiRB
register
Bits 6 to 0 in the UiRB
register are read as
bits 7 to 1. Bit 8 in the
UiRB register is read
as bit 0
(clock delay)
CKPH = 1
(3)
(2)