M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 175

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 151 of 587
14. DMACII
DMACII performs memory-to-memory transfer, immediate data transfer, and calculation transfer which transfers a
result of the addition of two data. DMACII transfer occurs in response to interrupt requests from the peripheral
functions.
Table 14.1 lists specifications of DMACII.
14.1
Table 14.1
NOTES:
14.1.1
DMACII request source
Transfer data
Transfer unit
Transfer space
Transfer address
Transfer mode
Chain transfer function
End-of-transfer interrupt
Set up the following registers and tables to activate DMACII.
When the DMAII bit is set to 1 (interrupt priority level 7 is used for DMACII transfer) and the FSIT bit to 0
(interrupt priority level 7 is used for normal interrupt), DMACII is activated by an interrupt request from any
peripheral functions with bits ILVL2 to ILVL0 in the Interrupt Control Register set to 111b (level 7).
Figure 14.1 shows the RLVL register.
1. When a destination address is 0FFFFh and a 16-bit data is transferred, it is transferred to addresses 0FFFFh
2. The actual transferable space varies depending on internal RAM capacity.
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•
•
•
•
RLVL register
DMACII Index
Interrupt Control Register of the peripheral functions triggering DMACII requests
The relocatable vector table of the peripheral functions triggering DMACII requests
IRLT bit in the IIOiIE register (i = 0 to 11) if using the intelligent I/O interrupt, CAN interrupt, INTj interrupt
(j = 6 to 8), UARTk (k = 5, 6) transmit, or UARTk receive interrupt. Refer to 11. Interrupts for details on the
IIOiIE register.
and 10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is
transferred to a given destination address.
DMACII Settings
RLVL Register
Item
DMACII Specifications
Interrupt requests generated by any peripheral functions with bits ILVL2 to ILVL0 in
the Interrupt Control Register set to 111b (level 7)
- Data in a memory location is transferred to another memory location
- Immediate data is transferred to a memory location (immediate data transfer)
- Data in a memory location (or immediate data) + data in another memory location
8 bits or 16 bits
64-Kbyte space in addresses 00000h to 0FFFFh
Fixed address: one specified address
Incremented address: address which is incremented by the transfer unit on each
successive access.
(Selectable for source address and destination address individually)
Single transfer, burst transfer, multiple transfer
Address indicated by an interrupt vector for DMACII index is replaced when a
transfer counter reaches zero
Interrupt occurs when a transfer counter reaches zero
(memory-to-memory transfer)
is transferred to the other memory location (calculation transfer)
Specification
(1)(2)
14. DMACII