M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 409

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 385 of 587
22.4.2
Table 22.18
Data format
Baud rate
Transmit start
condition
Receive start
condition
Interrupt request
generation timing
Error detection
Selectable
function
Table 22.18 lists specifications of UART mode. Table 22.19 lists pin settings. Figures 22.51 and 22.52 show
register settings. Figure 22.53 shows an example of a transmit operation. Figure 22.54 shows an example of a
receive operatio
Item
Clock Asynchronous (UART) Mode (Group 1)
UART Mode Specifications
n.
• Start bit: 1 bit long
• Parity bit: selectable among odd, even, or none
• Stop bit: selectable from 1 bit or 2 bits long
• The CKDIR bit in the G1MR register is set to 0 (internal clock)
• Bits CCS3 and CCS2 in the CCS register is set to 00b (Clock generated with waveform
The internal transmit clock is generated in phase-delayed waveform output mode of the channel 3.
The internal receive clock is generated by performing both the time measurement and phase-
delayed waveform output in the channel 2.
Set registers associated with the waveform generation function and the G1MR register. Then
wait for one or more internal transmit clock cycles before all of the following conditions are met to
start the transmit operation.
Set registers associated with the waveform generation function and the G1MR register. Then
wait for one or more internal receive clock cycles before all of the following conditions are met to
start the receive operation.
Transmit interrupt (The IRS bit in the G1MR register selects one of the following):
Receive interrupt:
• Overrun error
• Framing error
• Parity error
Each error flag is updated when the data is transferred from the receive shift register to the G1RB
register every time a receive operation is completed.
• LSB first or MSB first
• Data length: 8 bits long
The SIO1TR bit in the IIO3IR register becomes 1 (interrupt requested) when a transmit interrupt
request is generated (Refer to Figure 11.18).
The SIO1RR bit in the IIO2IR register becomes 1 (interrupt requested) when a receive interrupt
request is generated (Refer to Figure 11.18).
generation function)
•The TE bit in the G1CR register is set to 1 (transmit operation enabled)
•The TI bit in the G1CR register is 0 (data in the G1TB register)
•The RE bit in the G1CR register is set to 1 (receive operation enabled)
•Detecting the start bit (“L” level)
•When the IRS bit is set to 0 (no data in the GiTB register):
•When the IRS bit is set to 1 (transmit operation completed):
•When data is transferred from the receive shift register to the G1RB register (receive operation
Overrun error occurs when the preceding bit of the final stop bit of the next data (the first stop
bit when selecting 2 stop bits) is received before reading the G1RB register. If an overrun error
occurs, a read from the G1RB register returns an undefined value.
Framing error occurs when the number of the stop bits set by the STPS bit in the G1MR register
is not detected.
Parity error occurs when parity is enabled and the received data does not have the correct even
or odd parity set by the PRY bit in the G1MR register.
Data is transmitted or received from either bit 0 or bit 7.
When data is transferred from the G1TB register to the transmit shift register (transmit
operation started)
When the final stop bit is output from the transmit shift register
completed)
2(n + 2)
fBT1
n: Setting value of the G1PO0 register (0006h to FFFDh)
Specification