M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 413

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 389 of 587
22.4.3
Table 22.20
Input data format
Output data format
Transfer clock
I/O method
Bit stuffing
Flag sequence detection
Abort sequence detection Write the abort sequence “FEh” to the GiCMPj register (j = 0, 1) and the masked data
CRC
Data processing start
condition
In HDLC data processing mode, bit stuffing, flag sequence detection, abort sequence detection and CRC
calculation are available for HDLC data processing. In this mode, the MCU is unable to input or output data in no-
return-to-zero-invert (NRZI) format (No pin is used). f1, f8 or f2n can be selected as the group 0 transfer clock. f1,
f8, f2n or the clock generated in the channel 0 or 1 can be selected as the group 1 transfer clock.
To generate HDLC frame data, write source data to the GiTB register (i=0,1). The data conversion result is stored
into the GiTO register. If data is in the GiTO register, the conversion is stopped. The conversion is resumed by
reading the GiTO register. The HDLC data processing is performed even no data in the GiTB register. A CRC
value is calculated every time one bit is converted.
To generate source data, write HDLC frame data to the GiRI register. The data in the GiRI register is transferred to
the shift register. HDLC data processing starts when the value in the shift register matches the value in the GiCMP3
register (7Eh). The data conversion result is stored into the GiRB register.
Tables 22.20 and 22.21 list specifications of the HDLC data processing mode. Tables 22.22 and 22.23 list clock
settings. Table 22.24 lists register settings.
Item
HDLC Data Processing Mode (Group 0 and Group 1)
Specifications of the HDLC Data Processing Mode (1/2)
See Tables 22.22 and 22.23
When HDLC frame data is generated, a “0” is inserted after five continuous “1’s”.
8-bit data fixed, bit alignment is optional
8-bit data fixed
• When HDLC frame data is generated from source data:
• When source data is generated from HDLC frame data:
When source data is generated, a “0” is deleted after five continuous “1’s”.
Write the flag sequence “7Eh” to the GiCMP3 register. When the GiDR register matches
the GiCMP3 register, a special communication function interrupt is generated. (The
SRTiR bit in the IIO4IR register becomes 1.)
“01h” to the GiMSKj register. When the GiDR register and the GiCMPj register are
compared and all the non-masked bits are matched, a special communication function
interrupt is generated. (The SRTiR bit in the IIO4IR register becomes 1.)
Bits CRC1 and CRC0 are set to 11b (X
The CRCV bit is set to 1 (set to FFFFh)
The following conditions are required to start HDLC frame data generation:
The following conditions are required to start source data generation:
A value set in the GiTB register (i=0,1) is converted with HDLC data processing and
transferred to the GiTO register.
A value set in the GiRI register is converted with HDLC data processing and
transferred to the GiRB register.
• When HDLC frame data is generated: CRC calculation result is stored into the
• When source data is generated: CRC calculation result is stored into the GiRCRC
• The TE bit in the GiCR register is set to 1 (transmit operation enabled)
• Data is written to the GiTB register
• The RE bit in the GiCR register is set to 1 (receive operation enabled)
• Data is written to the GiRI register
Initialization: The CRC calculation result is initialized when the GiDR register matches
Initialization: The CRC calculation result is initialized when the TE bit in the GiCR
GiTCRC register. The TCRCE bit in the GiETC register is set to 1 (transmit CRC
used).
register is set to 0 (transmit disabled).
register. The RCRCE bit in the GiERC register is set to 1 (receive CRC used).
the GiCMP3 register by comparing the flag sequence “7Eh” (The ACRC bit in the
GiEMR register is set to 1 (CRC is initialized)).
Specification
16
+X
12
+X
5
+1)