M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 461

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 437 of 587
Figure 23.28
Figure 23.29
For Standard ID
Registers CiGMRk, CiLMARk, and CiLMBRk (i = 0, 1, k = 0 to 4) are used for acceptance filtering.
By using these registers, users are able to select which messages to receive.
The CiGMRk register determines whether IDs in the message slots 0 to 13 are checked or not. The CiLMARk
register determines whether ID in the message slot 14 is checked or not. The CiLMBRk register determines
whether ID in the message slot 15 is checked or not.
NOTES:
Figure 23.28 shows individual mask registers and corresponding message slots. Figure 23.29 shows the
acceptance filtering.
Receive message ID
Standard ID0
Standard ID1
Standard ID10
•
•
1. Change the CiGMRk register while none of the message slots 0 to 13 has a receive request.
2. Change the CiLMARk register while the message slot 14 has no receive request.
3. Change the CiLMBRk register while the message slot 15 has no receive request.
4. When there are two or more receive message slots which have the matched ID with the received message,
When the bit in the CiGMRk, CiLMARk, or CiLMBRk register is set to 0, the corresponding bit (ID bit) in
the CANi message slot j’s (j = 0 to 15) standard ID0, standard ID1, or extended ID0 to extended ID2 is
masked in acceptance filtering. (The corresponding bit is assumed to have a matching ID.)
When the bit in the CiGMRk, CiLMARk, CiLMBRk register is set to 1, the corresponding ID bit is
compared with a received ID in acceptance filtering. When the received ID matches the ID set in the
message slot j, the receive data is stored into the message slot having the matched ID.
the received message is stored into the smallest-numbered message slot.
Individual Mask Registers and Message Slots
Acceptance Filtering
i = 0, 1
k = 0 to 4
ID set in the
message slot
SID0
SID1
SID10
CiLMARk register
CiLMBRk register
CiGMRk register
CiGMR register
CiLMAR register
CiLMBR register
SID0M
SID1M
SID10M
Message slot 13
Message slot 14
Message slot 15
Message slot 0
to
Value of the mask bit
0: Whether a receive message ID is matched
1: Whether a receive message ID is matched
Acceptance verify signal
0: Receive message is ignored
1: Receive message is stored into a
is handled as "don't care" (or masked)
is verified
(Message is stored into no message slot)
message slot having a matched ID
Acceptance verify signal
23. CAN Module