M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 317

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 293 of 587
18. A/D Converter
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has one 10-bit successive approximation A/D converter with a
capacitance coupled amplifier.
The results of A/D conversion are stored into the AD0i registers (i = 0 to 7) corresponding to the selected pins. When
using DMAC operating mode, the conversion results are stored only into the AD00 register.
Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the A/D converter. Figures
18.2 to 18.6 show registers associated with the A/D converter.
Table 18.1
NOTES:
A/D conversion method
Analog input voltage
Operating clock φAD
Resolution
Operating modes
Analog input pins
A/D conversion start condition
Conversion rate per pin
1. The φAD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5 V.
2. AVCC = VCC1 ≥ VCC2
NOTE
The φAD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5 V.
Without the sample and hold function, the φAD frequency must be 250 kHz or higher.
With the sample and hold function, the φAD frequency must be 1 MHz or higher.
AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1) ≤ VCC1,
AD input (AN0_0 to AN0_7, AN2_0 to AN2_7) ≤ VCC2
The 144-pin package is described as an example in this chapter.
Pins AN15_0 to AN15_7 are not provided in the 100-pin package.
Item
A/D Converter Specifications
(2)
(1)
Successive approximation (with capacitance coupled amplifier)
0 V to AVCC (VCC1)
fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8
Selectable from 8 bits or 10 bits
• One-shot mode
• Repeat mode
• Single sweep mode
• Repeat sweep mode 0
• Repeat sweep mode 1
• Multi-port single sweep mode
• Multi-port repeat sweep mode 0
144 pin package: 34 pins
100 pin package: 26 pins
• Software trigger
• External trigger (retrigger is enabled)
• Hardware trigger (retrigger is enabled)
• Without sample and hold function
• With sample and hold function
The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts).
When the falling edge is detected at the ADTRG pin after the ADST bit is set to 1.
Timer B2 interrupt request of the three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1.
8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7),
AN2 (AN2_0 to AN2_7), and AN15 (AN15_0 to AN15_7)
2 extended input pins (ANEX0 and ANEX1)
8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7),
AN2 (AN2_0 to AN2_7)
2 extended input pins (ANEX0 and ANEX1)
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
Specification
18. A/D Converter