M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 351

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 327 of 587
Figure 22.6
Group 1 Time Measurement Register i (i = 0 to 7)
Group 1 Waveform Generation Control Register i (i = 0 to 7)
b15
b7 b6 b5 b4
NOTES:
1. SR waveform output mode is enabled only in even channels. In SR waveform output mode, the setting for the corresponding odd
2. To perform the UART receive operation in group 1, set the G1POCR2 register to 0000 0110b.
3. To use the ISTXD1 pin, set bits MOD2 to MOD0 in the G1POCR0 register to 111b. To use the ISCLK1 pin as output, set bits
4. The BTRE bit is available only in the G1POCR0 register. Set the bit 6 in registers G1POCR1 to G1POCR7 to 0.
5. If the INV or IVL bit is written while outputting waveform, the value written takes effect immediately on the output waveform.
6. When the BTRE bit is set to 1, set bits BCK1 and BCK0 in the G1BCR0 register to 11b (f1), and bits UD1 and UD0 in the
b8
channel (the channel followed by the even channel) is ignored. SR waveform can be output from even channels, and not from
odd channels.
MOD2 to MOD0 in the G1POCR1 register to 111b. Do not set bits MOD2 to MOD0 in registers G1POCR2 to G1POCR7 to 111b.
G1BCR1 register to 00b (counter increment mode).
b3
b7
b2
G1TM0 to G1TM7 Registers, G1POCR0 to G1POCR7 Registers
b1
b0
b0
The base timer value is stored every time measurement is
performed
Bit Symbol
MOD0
MOD1
MOD2
BTRE
RLD
(b3)
Symbol
G1TM0 to G1TM2
G1TM3 to G1TM5
G1TM6, G1TM7
Symbol
G1POCR0
G1POCR1 to G1POCR3
G1POCR4 to G1POCR7
INV
IVL
−
Operating mode select bits
Unimplemented.
Write 0. Read as undefined value.
Output level select bit
G1POi register value reload
timing select bit
Base timer reset timing
select bit
Inverted output function
select bit
(4)
(5)
Bit Name
Function
(5)
Address
0101h - 0100h, 0103h - 0102h, 0105h - 0104h
0107h - 0106h, 0109h - 0108h, 010Bh - 010Ah
010Dh - 010Ch, 010Fh - 010Eh
Address
0110h
0111h, 0112h, 0113h
0114h, 0115h, 0116h, 0117h
b2 b1 b0
0 0 0: Single waveform output mode
0 0 1: SR waveform output mode
0 1 0: Phase-delayed waveform output mode
0 1 1: Do not set to this value
1 0 0: Do not set to this value
1 1 0: Do not set to this value
1 1 1: Use communication function output
0: "L" output
1: "H" output
0: Reload when written
1: Reload when the base timer is reset
0: Base timer is reset when the bit 15 overflows
1: Base timer is reset when the bit 9 overflows
0: Output not inverted
1: Output inverted
Function
Setting Range
(2)
(1)
−
(3)
After Reset
Undefined
Undefined
Undefined
After Reset
0000 X000b
0X00 X000b
0X00 X000b
(6)
22. Intelligent I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
−