M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 595

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 571 of 587
28.9.3
28.9.3.1
28.9.3.2
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The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 0 (count stops) after reset. Set the TBiS
bit to 1 (count starts) after selecting timer operating mode and setting the TBi register.
Bits TB2S to TB0S are bits 7 to 5 in the TABSR register. Bits TB5S to TB3S are bits 7 to 5 in the TBSR
register.
The TBi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. When the TBi register is set while a counter is stopped, the setting value can be read
until a counter is started.
To set the MR3 bit to 0 (no overflow has occurred), wait for one or more count source cycles to write to the
TBiMR register after the MR3 bit becomes 1, while the TBiS bit is set to 1.
(Technical update: TN-M16C-75-0110)
Use the IR bit in the TBiIC register to detect overflow. The MR3 bit is used only to determine an interrupt
request source within the interrupt routine.
When the first valid edge is input after the count starts, an undefined value is transferred to the reload
register. At this time, the timer Bi interrupt request is not generated.
The counter value is undefined when the count starts. Therefore, the MR3 bit may become 1 (overflow) and
causes a timer Bi interrupt request to be generated before a valid edge is input.
The IR bit may become 1 (interrupt requested) by changing bits MR1 and MR0 in the TBiMR register after
the count starts. If the same value is written to bits MR1 and MR0, the IR bit is not changed.
Pulse width is repeatedly measured in pulse width measurement mode. Determine by a program whether
the measurement result is high (“H”) or low (“L”).
If an overflow and a valid edge input occur simultaneously in pulse period measurement mode, an interrupt
request is generated only once, which results in the valid edge not being recognized. Do not let an overflow
occur.
In pulse width measurement mode, determine whether an interrupt source is a valid edge input or an
overflow by reading the port level in the TBi interrupt routine.
Timer B
Timer B (Pulse Period/Pulse Width Measurement Mode)
Timer B (Timer Mode, Event Counter Mode)
28. Usage Notes