M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 227

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 203 of 587
Figure 16.7
Timer B2 Interrupt Generation Frequency Set Counter
Timer B2 Special Mode Register
b7
b7
0
b6 b5 b4
0
b6 b5 b4 b3
NOTE:
NOTES:
0
1. Set the TB2SC register after the PRC1 bit in the PRCR register is set to 1 (write enable).
1. Read-modify-write instructions cannot be used to set the ICTB2 register. Refer to Usage Notes for details.
2. If the INV01 bit in the INVC0 register is set to 1, set the ICTB2 register while the TB2S bit is set to 0 (count stops). If the INV01
bit is set to 0, do not set the ICTB2 register when timer B2 underflows, regardless of the TB2S bit setting.
0
b3
0
b2
TB2SC Register, ICTB2 Register
0
b1
0
b0
b0
Unimplemented.
Write 0. Read as undefined value.
Bit Symbol
- When the INV01 bit in the INVC0 register is set to 0 (the ICTB2
- When bits INV01 and INV00 are set to 10b (the ICTB2 counter
- When bits INV01 and INV00 are set to 11b (the ICTB2 counter
PWCON
counter increments every timer B2 underflows) and a setting
value is n, the timer B2 interrupt request is generated every n-th
timer B2 underflow.
increments when the timer B2 underflow at the rising edge of the
timer A1 reload control signal) and a setting value is n, the first
timer B2 interrupt request is generated at the (2n-1)th timer B2
underflow. From the 2nd time on, the request is generated every
2n-th timer B2 underflow.
increments when the timer B2 underflow occurs at the falling edge
of the timer A1 reload control signal) and a setting value is n;
(b7-b1)
• When n > 1, the first timer B2 interrupt request is generated at
• When n = 1, the timer B2 interrupt request is generated every
the (2n-2)th timer B2 underflow. From the 2nd time on, the
request is generated every 2n-th timer B2 underflow.
2n-th timer B2 underflow.
Symbol
TB2SC
Symbol
ICTB2
−
Timer B2
reload timing switch bit
Reserved bits
Bit Name
(1)
Function
Address
030Dh
Address
035Eh
0: Timer B2 underflow
1: Timer B2 underflow at the rising edge of the
Set to 0
timer A1 reload control signal
(every odd-numbered timer B2 underflow)
16. Three-Phase Motor Control Timer Function
(1, 2)
Function
Setting Range
1 to 15
After Reset
Undefined
After Reset
00h
RW
RW
RW
RW
WO
−