M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 155

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 131 of 587
11.11.1 IIOiIE Register
11.11.2 IIOiIR Register
11.11.3 IIOiIC (CANjIC) Register
Table 11.7
NOTES:
CAN00
CAN01
CAN02
CAN10
CAN11
CAN12
CAN1 Wake-up
To configure for intelligent I/O interrupts, use IIOiIE register (i = 0 to 11), IIOiIR register, and IIOiIC (CANjIC (j =
0 to 5)) register.
Table 11.7 lists registers used for CAN interrupts, UART5 and UART6 transmit/receive interrupts, and INT6 to
INT8 interrupts. Figure 11.20 shows an interrupt request bit timing with multiple interrupt sources. Figure 11.21
shows an interrupt routine example.
CAN Interrupt
1. Only CAN00 to CAN02 interrupts can be used in M32C/87A. No CAN interrupt is provided in M32C/87B.
2. The IIO9IC register and the CAN0IC register share the same address. So do the IIO10IC register and CAN1IC
register, the IIO11IC register and the CAN2IC register, the IIO0IC register and the CAN3IC register, the IIO1IC
register and the CAN4IC register, and the IIO5IC register and the CAN5IC register.
•
•
•
•
IRLT bit
Set to 1 to use interrupt requests from individual peripheral functions for interrupts. Set to 0 to use them for
DMA or DMACII trigger sources.
Interrupt enable bit
Set the interrupt enable bit corresponding to the interrupt to be used, to 1 (interrupt enabled) after setting
the IRLT bit.
Interrupt request flag
The interrupt request flag becomes 1 (interrupt requested) when an interrupt request is generated. This flag
does not automatically become 0 when the interrupt request is acknowledged. Use AND or BCLR
instruction to set it to 0 (interrupt not requested) in the interrupt routine. If any of these flags remains 1, the
IR bit in the IIOiIC (CANjIC) register does not become 1 when an interrupt request is generated in the same
register. (Interrupt does not occur.)
If an interrupt request is generated while writing a 0 to the corresponding interrupt flag, the flag may not be
cleared to 0. In this case, keep writing a 0 until 0 is read.
IR bit
The IR bit in the IIOiIC register becomes 1 (interrupt requested), if all the enabled request flags in the
corresponding IIOiIR register are set to 0, and an interrupt request corresponding to one of these flags is
generated. The IR bit automatically becomes 0 when the interrupt is acknowledged.
Interrupts shared with Intelligent I/O Interrupt
Registers Used for CAN interrupts, UART5 and UART6 transmit/receive interrupts,
and INT6 to INT8 interrupts
(1)
UART6 receive
UART6 transmit
−
UART5 receive
UART5 transmit
−
Transmit/receive
UART
INT6
INT7
INT8
−
−
−
INT Interrupt
IIO9IE
IIO10IE
IIO11IE
IIO0IE
IIO1IE
IIO5IE
Registers to be Used
IIO9IR
IIO10IR
IIO11IR
IIO0IR
IIO1IR
IIO5IR
IIO9IC (CAN0IC)
IIO10IC (CAN1IC)
IIO11IC (CAN2IC)
IIO0IC (CAN3IC)
IIO1IC (CAN4IC)
IIO5IC (CAN5IC)
(2)
11. Interrupts