M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 362

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 338 of 587
Figure 22.15
(1) Group 1
(2) Group 2
Reset signal by matching
Reset signal by matching
communication function
Two phase pulse input
i = 1, 2
BCK1 and BCK0, IT: Bits in the GiBCR0 register
RST1, RST2, BTS: Bits in the GiBCR1 register
RST0: Bit in the G2BCR1 register
BTRE: Bit in the G1POCR0 register
BT1S, BT2S: Bits in the BTSR register
NOTE:
the INT0 or INT1 pin
the G1PO0 register
the G2PO0 register
1. The divider is reset when both the BTiS and BTS bits are set to 0.
the base timer with
the base timer with
group 1 base timer
Reset signal from
"L" is applied to
Request from
Base Timer Block Diagram
f1
BT1S
BT2S
BTS
BTS
BCK1 and BCK0
f1
11
BCK1 and BCK0
RST1
RST2
RST0
RST1
RST2
11
10
Divider 2(n+1)
Divider 2(n+1)
(Note 1)
(Note 1)
Base timer reset
Base timer reset
fBT1
fBT2
Base Timer
Base Timer
b0 to b13
b9
b14 b15
b14 b15
0
1
BTRE
22. Intelligent I/O (Base Timer)
1
0
0
1
Overflow signal
Overflow signal
IT
IT
Base timer
Base timer
interrupt request
interrupt request