M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 118

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 94 of 587
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
The CPU clock is used to operate the CPU and also used as the count source for the watchdog timer. After reset, the
CPU clock is the main clock divided by eight. The bus clock (BCLK) has the same frequency as the CPU clock and
can be output from the BCLK pin in memory expansion mode or microprocessor mode. Refer to 9.4 Clock Output
Function for details.
The main clock, sub clock, on-chip oscillator clock, or PLL clock can be selected as the clock source for the CPU
clock.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the clock source for the CPU clock, the
selected clock source divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 becomes the CPU clock. Bits MCD4
to MCD0 in the MCD register select the clock division. When the MCU enters stop mode or low-power
consumption mode, bits MCD4 to MCD0 are set to 01000b (divide-by-8 mode). Therefore, when the CPU clock
source is switched to the main clock next time, the CPU clock is the main clock divided by eight. Refer to 9.5
Power Consumption Control for details.
The peripheral function clocks are used to operate the peripheral functions excluding the watchdog timer. The
clock selected by the CM17 bit in the CM1 register and the CM21 bit in the CM2 register (any of the main clock,
PLL clock, or on-chip oscillator clock) becomes the peripheral function clock source (fPFC).
f1, f8 and f32 are fPFC divided by 1, 8, or 32.
Bits PM27 and PM 26 in the PM2 register select the f2n clock source from fPFC, XIN clock (fXIND), and the
on-chip oscillator clock (fROC). Bits CNT3 to CNT0 in the TCSPR register select the f2n division. (n = 1 to 15.
No division when n = 0.)
When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait
mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fPFC
stops. When bits PM27 and PM26 in the PM2 register are set to 10b (on-chip oscillator clock is selected for the
f2n clock source), f2n does not stop in wait mode.
f1, f8, and f2n are used to operate the serial interface and also is used as the count source for timer A and
timer B. f1 is also used to operate the intelligent I/O and CAN modules.
The CLKOUT pin outputs f8 and f32. Refer to 9.4 Clock Output Function for details.
fAD is used to operate the A/D converter and has the same frequency as fPFC.
When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait
mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fAD stops.
fC32 is the sub clock divided by 32. fC32 is used as the count source for timer A and timer B. fC32 is available
if the sub clock is running.
fCAN has the same frequency as the main clock. It is the clock for the CAN module only.
CPU Clock and BCLK
Peripheral Function Clock
f1, f8, f32, and f2n
fAD
fC32
fCAN
9. Clock Generation Circuits