M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 239

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 215 of 587
17.1
Figure 17.1
CTSi / RTSi
Figure 17.1 shows a UART0 to UART4 block diagram. Figures 17.2 to 17.10 show the registers associated with
UART0 to UART4. Refer to the tables listing for register and pin settings in each mode.
F2n
SP
i = 0 to 4
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, and CKDIR: bits in the UiMR register
CLK1 and CLK0, CKPOL, CRD, and CRS: bits in the UiC0 register
UiERE: bit in the UiC1 register
m = Setting value of the UiBRG register
NOTES:
f1
f8
SP
(1)
RXDi
RXDi
CLK1 and CLK0
CLKi
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Select either Input/output port (CLKi input) or CLKi output in the Function Select Registers. (Refer to the chapter Programmable
3. Select either Input/output port or RTSi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports .)
UART0 to UART4
00
01
10
I/O Ports .)
0
1
SP
STPS
Function Select
Register
Function Select
Register
CKDIR
UART0 to UART 4 Block Diagram
0
1
0
1
SP
STPS
0
CLKi input
CLKi output
0
1
(2)
(3)
IOPOL
0
RTSi output
CTSi input
SMD2 to SMD0
SMD2 to SMD0
1/(m+1)
register
UiBRG
PAR
PAR
0
switching
switching
CKPOL
0
Polarity
Polarity
0
1
0
1
PRYE
PRYE
CRD
CRS
0
100
101
110
001
100
101
110
001
0
0
1/16
1/16
1/2
D8
D8
b8
b8
High-order bits of data bus
Low-order bits of data bus
110
110
001
101
001
101
100, 101, 110
100, 101, 110
0
1
CKDIR
SMD2 to SMD0
b7
b7
001
001
001
101
110
001
101
110
Logic inverse circuit + MSB/LSB conversion circuit
Logic inverse circuit + MSB/LSB conversion circuit
100
100
D7
D7
D6
D6
b6
b6
output circuit
control circuit
control circuit
Error signal
Transmit
Receive
UARTi transmit shift register
UARTi receive shift register
17. Serial Interfaces (UART0 to UART4)
D5
D5
b5
b5
D4
D4
b4
b4
D3
D3
b3
b3
0
1
UiERE
Receive
clock
Transmit
clock
D2
D2
b2
b2
D1
D1
b1
b1
Transmit/
receive
0
1
unit
D0
D0
b0
b0
IOPOL
UiTB register
UiRB register
TXDi
TXDi