M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 404

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 22. Intelligent I/O (Group 0 and 1 Communication Function)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 380 of 587
n: Setting value of the G1PO0 register (0001h to FFFDh)
Table 22.16
NOTES:
Table 22.17
NOTES:
P7_3
P7_4
P7_5
P7_6
P7_7
P8_0
P11_0 ISTXD1 Output
P11_1 ISCLK1 Input
P11_2 ISRXD1 Input
P15_0 ISTXD0 Output
P15_1 ISCLK0 Input
P15_2 ISRXD0 Input
f8
f2n
Input to ISCLK1 pin
Port
2(n+2)
1. The serial clock is generated in phase-delayed waveform output mode of the channel 3. The baud rate is set
2. Bits CNT3 to CNT0 in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
3. The serial clock is set to fBT1 divided by six or lower frequency. Additionally, meet the timing requirements,
1. Set registers PS1, PS2, PS5, and PS9 after setting the other registers.
2. Set bits MOD2 to MOD0 in the corresponding register to 111b (use communication function output).
3. After an operating mode is selected in the GiMR register and the pin function is set in the Function Select
fBT1
(2)
Serial Clock
using the function, which is to reset a base timer when the value in the G1PO0 register matches the value of a
base timer.
which are shown on Tables 27.25 and 27.48 Intelligent I/O communication function (Groups 0 and 1) in the
chapter 27. Electrical Characteristics.
Registers, the ISTXDi pin outputs an “H” signal when the OPOL bit is set to 0 (No ISTXD output polarity invert)
or the ISTXDi pin outputs an “L” signal when the OPOL bit is set to 1 (ISTXD output polarity invert) until a
transmit operation starts.
ISTXD1 Output
ISCLK1 Input
ISCLK1 Output
ISRXD1 Input
ISTXD0 Output
ISCLK0 Input
ISCLK0 Output
ISRXD0 Input
ISCLK1 Output
ISCLK0 Output
Function
Clock Settings (Group 1)
Pin Settings in Clock Synchronous Mode (Groups 0 and 1)
(NOTE 1)
(3)
(3)
(3)
(3)
(3)
G1POCR0
−
G1POCR1
−
−
−
−
−
G1POCR0
−
G1POCR1
−
−
−
−
−
Registers
G1POCR0
G1POCR1
G1MR Register
CKDIR Bit
(2)
0
0
0
1
−
IPS1=0
−
IPS1=0
−
IPS0=0
−
IPS0=0
−
IPS1=1
−
IPS1=1
−
IPS0=1
−
IPS0=1
Register
IPS
−
PD7_4=0
−
PD7_5=0
−
PD7_7=0
−
PD8_0=0
−
PD11_1=0
−
PD11_2=0
−
PD15_1=0
−
PD15_2=0
PD11,PD15
PD7, PD8,
Registers
Bits CCS3 and CCS2
CCS Register
00b
11b
10b
−
−
−
PSD1_4=0 PSC_4=1 PSL1_4=0
−
PSD1_6=0 PSC_6=0 PSL1_6=0
−
−
−
−
−
−
−
−
−
−
−
Register
PSD1
Bit Setting
PSC_3=1 PSL1_3=0
−
−
−
−
−
−
−
−
−
−
−
−
−
Register
PSC
−
−
−
PSL1_7=0
−
PSL5_0=0
−
PSL5_1=0
−
PSL9_0=0
−
PSL9_1=0
−
Registers
PSL1,
PSL5,
PSL9
PS1_3=1
PS1_4=0
PS1_4=1
PS1_5=0
PS1_6=1
PS1_7=0
PS1_7=1
PS2_0=0
PS5_0=1
PS5_1=0
PS5_1=1
PS5_2=0
PS9_0=1
PS9_1=0
PS9_1=1
−
Registers
PS1, PS2,
PS5, PS9
(1)