M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 289

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 265 of 587
Figure 17.32
Receive operation starts when the start bit is detected.
Read the UiRB register when the receive operation is completed.
i = 0 to 4
NOTES:
Transmit operation starts by writing data to the UiTB register
1. Set to 1 in the direct format, and set to 0 in the inverse format.
2. Set to 0 in the direct format, and set to 1 in the inverse format.
3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
4. Determine whether an "L" is output from the TXDi pin by reading the port that shares a pin with the RXDi pin in the receive
I flag = 0
UiMR register: bits SMD2 to SMD0 = 101b
UiSMR register = 00h
UiSMR2 register = 00h
UiSMR3 register = 00h
UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0
UiBRG register = m
UiC1 register: TE bit = 0
SiTIC register: bits ILVL2 to ILVL0
SiRIC register: bits ILVL2 to ILVL0
I flag = 1
UiC1 register: TE bit = 1
operation complete interrupt routine. When an "L" is output, wait for one clock cycle to read the UiRB register.
Pin setting in the Function Select Registers
Register Settings in SIM Mode
CRD bit = 1
NCH bit = 1
CKPOL bit = 0
UFORM bit
RE bit = 0
UiIRS bit = 1
UiRRM bit = 0
UiLCH bit
UiERE bit = 1
RE bit = 1
CKDIR bit = 0
STPS bit = 0
PRY bit
PRYE bit = 1
IOPOL bit = 0
IR bit = 0
IR bit = 0
Start initial setting
End initial setting
Interrupt disabled
UART mode: 8-bit data length
Select internal clock
Select 1 stop bit
Parity select bit
Parity enabled
UiBRG register count source select bits
CTS function disabled
N-channel open drain output
Bit order select bit
m = 00h to FFh
Transmit operation disabled
Receive operation disabled
Transmit completion as transmit interrupt source
Data logic select bit
Error signal output enabled
Transmit interrupt priority level select bits
Interrupt not requested
Receive interrupt priority level select bits
Interrupt not requested
Interrupt enabled
Transmit operation enabled
Receive operation enabled
(1)
(2)
Baud rate =
(2)
17. Serial Interfaces (UART0 to UART4)
16(m + 1)
fj
fj = f1, f8, f2n
(3)