M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 354

IC M32C/87 MCU FLASH 144LQFP

M3087BFLBGP#U5

Manufacturer Part Number
M3087BFLBGP#U5
Description
IC M32C/87 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet

Specifications of M3087BFLBGP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
121
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 330 of 587
Figure 22.9
Group 2 Base Timer Register
Group 2 Base Timer Control Register 0
b15
b7 b6 b5 b4
NOTES:
1. The base timer operates when its count source is selected using bits BCK1 and BCK0 in the G2BCR0 register. When both the
2. The G2BT register reflects the value of the base timer with a half fBT2 clock cycle delay.
b8
BT2S bit in the BTSR register and the BTS bit in the G2BCR1 register are set to 0, the base timer is placed in a reset state and
the count value remains 0000h. When either the BT2S or the BTS bit is set to 1, the count starts.
b3
b7
b2
G2BT Register, G2BCR0 Register
b1
b0
b0
⋅ While the base timer is counting:
⋅ While the base timer is in reset state:
Bit Symbol
When read, the base timer value is returned
When write, the count continues from the value written.
When read, undefined value is returned.
No value can be written.
BCK0
BCK1
DIV0
DIV1
DIV2
DIV3
DIV4
Symbol
G2BT
Symbol
G2BCR0
IT
Count source select bits
Count source divide ratio
select bits
Base timer interrupt
generation timing select bit
(1)
Bit Name
Function
Address
0161h - 0160h
Address
0162h
(2)
.
b1 b0
0 0: Clock stopped
0 1: Do not set to this value
1 0: Do not set to this value
1 1: f1
If setting value is n ( n = 0 to 31), the count
source is divided by 2( n + 1).
No division if n = 31.
( n = 0) 0 0 0 0 0: Divide-by-2
( n = 1) 0 0 0 0 1: Divide-by-4
( n = 2) 0 0 0 1 0: Divide-by-6
( n = 30) 1 1 1 1 0: Divide-by-62
( n = 31) 1 1 1 1 1: No division
0: When bit 15 is changed from 1 to 0
1: When bit 14 is changed from 1 to 0
b6 b5 b4 b3 b2
:
Function
0000h to FFFFh
Setting Range
After Reset
Undefined
After Reset
00h
22. Intelligent I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW

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