M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 486

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 462 of 587
25.6
25.7
25.8
25.9
25.10 Input Function Select Register (IPS, IPSA, and IPSB Registers)
25.11 Analog Input and Other Peripheral Function Input
Figure 25.18 shows registers PSD1 and PSD2.
When multiple peripheral function outputs are assigned to a single pin, registers PSD1 and PSD2 select which
peripheral function output to use.
Figure 25.19 shows registers PSE1 and PSE2.
When multiple peripheral function outputs are assigned to a single pin, registers PSE1 and PSE2 select which
peripheral function output to use.
Figures 25.20 to 25.23 show registers PUR0 to PUR4.
Registers PUR0 to PUR4 select whether the ports, divided into groups of four, are pulled up or not. Set the bit in
registers PUR0 to PUR4 to 1 (pull-up) and the bit in the PDi register to 0 (input mode) to pull-up the corresponding
port.
In memory expansion mode and microprocessor mode, set bits, corresponding to the bus control pins (P0 to P5), in
registers PUR0 and PUR1 to 0 (no pull-up). P0, P1, and P4_0 to P4_3 can be pulled up when they are used as input
ports in memory expansion mode and microprocessor mode.
Figure 25.24 shows the PCR register.
The PCR register selects either CMOS output or N-channel open drain output as port P1 output format. When the
PCR0 bit is set to 1, P channel in the CMOS port is turned off at all times and in result port P1 becomes N-channel
open drain output. This is, however, pseudo open drain. Therefore, the absolute maximum rating of the input
voltage is from -0.3 V to VCC2 + 0.3 V.
To use port P1 as data bus in memory expansion mode and microprocessor mode, set the PCR0 bit to 0 (CMOS
output). When port P1 is used as a port in memory expansion mode and microprocessor mode, set the output format
using the PCR0 bit.
Figures 25.24 to 25.25 show registers IPS, IPSA, and IPSB.
Registers IPS and IPSA determine which pins are used as input pins for intelligent I/O or CAN.
Refer to 25.11 Analog Input and Other Peripheral Function Input for information on the IPS2 bit in the IPS
register and the IPSB register.
Bits PSL3_3 to PSL3_6 in the PSL3 register, the PSC_7 bit in the PSC register, the IPS2 bit in the IPS register, and
bits IPSB_0 to IPSB_7 in the IPSB register are used to separate peripheral function inputs from analog input/
output. If the analog I/O shares the pin with other peripheral function inputs, a through current may flow to the
peripheral function inputs when an intermediate voltage is applied to the pin.
To use the analog I/O (DA0, DA1, ANEX0, ANEX1, AN_4 to AN_7 or AN15_0 to AN15_7), set the
corresponding bit to 1 (analog I/O), and disconnect the peripheral function inputs to prevent an intermediate
voltage from being applied to the peripheral function inputs.
When bits PSL3_3 to PSL3_6 (for P9_3 to P9_6), the IPS2 bit, and bits IPSB_0 to IPSB_7 (for P15_0 to P15_7)
are set to 1, the input buffer for the peripheral functions except for the port function is disconnected.
For P10_4 to P10_7 (AN_4 to AN_7/KI0 to KI3), when the PSC_7 bit is set to 1, the input buffer for the peripheral
functions including the port function is disconnected and ports P10_4 to P10_7 are read as undefined. Also, the IR
bit in the KUPIC register remains unchanged as 0 (interrupt not requested) even if KI0 to KI3 pin input levels are
changed.
Set the corresponding bit to 0 (except analog I/O) when analog I/O is not used.
Function Select Register D (PSD1 and PSD2 Registers)
Function Select Register E (PSE1 and PSE2 Registers)
Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)
Port Control Register (PCR Register)
25. Programmable I/O Ports