M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 597

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 573 of 587
28.11 Serial Interfaces
28.11.1 Changing UiBRG Register (i = 0 to 6)
28.11.2 Clock Synchronous Mode
28.11.3 UART Mode
28.11.4 Special Mode 1 (I
28.11.2.1 Selecting External Clock
28.11.2.2 Receive Operation
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Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. When bits CLK1 and CLK0 are
changed, set the UiBRG register again.
If an external clock is selected, meet the following conditions while the external clock is held “H” when the
CKPOL bit in the UiC0 register (i = 0 to 6) is set to 0 (transmit data output at the falling edge and receive data
input at the rising edge of the serial clock), or while the external clock is held “L” when the CKPOL bit is set to
1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock)
Set the UmERE bit in the UmC1 register after setting the UmMR register.
To generate the start condition, stop condition, or restart condition, set the STSPSEL bit in the UmSMR4
register to 0. Then, wait for a half clock cycle of the serial clock or more to change individual condition
generation bit (the STAREQ bit, STPREQ bit, or RSTAREQ bit) from 0 to 1.
(Technical update: TN-16C-130A/EA)
In clock synchronous mode, the serial clock is controlled by the transmit control circuit. Set the UARTi-
associated registers for a transmit operation as well, even if the MCU is used only for receive operation.
Dummy data is output from the TXDi pin while receiving if the TXDi pin is set to output mode.
If data is received continuously, an overrun error occurs when the RI bit in the UiC1 register is 1 (data in the
UiRB register) and the seventh bit of the next data is received in the UARTi receive shift register. And the
OER bit in the UiRB register becomes 1 (overrun error). In this case, a read from the UiRB register returns
undefined values. If an overrun error occurs, the IR bit in the SmRIC register (m = 0 to 4), the U5RR in the
IIO0IR register, or U6RR bit in the IIO9IR register is not changed to 1.
The following two conditions must be satisfied to use continuous receive mode (UiRRM bit is set to 1).
To receive data continuously under the other conditions, set the UiRRM bit to 0 (continuous receive mode
disabled), and write dummy data to the UiTB register every time a receive operation is completed.
The RE bit setting is not required for a transmit-only operation.
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(1) The CKDIR bit in the UiMR register is set to 1 (external clock).
(2) The RTS function is not used.
Set the TE bit in the UiC1 register to 1 (transmit operation enabled).
Set the RE bit in the UiC1 register to 1 (receive operation enabled).
The TI bit in the UiC1 register is 0 (data in the UiTB register).
2
C Mode)
28. Usage Notes