M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 165

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 141 of 587
Table 13.2
NOTES:
b4 b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.
2.
3.
4.
5.
6.
7.
8.
9.
Setting Value
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
When the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request cannot be
generated by an input signal to the INT3 pin.
The falling edge or both edges of input signal to the INTi pin can be a DMA request source. It is not affected by the INT interrupts (bits
POL and LVS in the INTiIC register, the IFSR register) and vice versa.
To switch between the UARTj receive interrupt and ACK interrupt (j = 0 to 4), use the IICM bit in the UiSMR register and IICM2 bit on
the UiSMR2 register. To use the ACK interrupt, set the IICM bit to 1 (I
The same setting is used for a CAN10 interrupt request and a UART5 receive interrupt request.
The same setting is used for a CAN11 interrupt request and a UART5 transmit interrupt request.
The same setting is used for a CAN12 interrupt request.
The same setting is used for a CAN00 interrupt request, an INT6 interrupt request, and a UART6 receive interrupt request.
The same setting is used for a CAN01 interrupt request, an INT7 interrupt request, and a UART6 transmit interrupt request.
The same setting is used for a CAN02 interrupt request and INT8 interrupt request.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DMiSL Register (i = 0 to 3) Function
Software trigger
Falling edge of INT0
Both edges of INT0
Timer A0 interrupt request
Timer A1 interrupt request
Timer A2 interrupt request
Timer A3 interrupt request
Timer A4 interrupt request
Timer B0 interrupt request
Timer B1 interrupt request
Timer B2 interrupt request
Timer B3 interrupt request
Timer B4 interrupt request
Timer B5 interrupt request
UART0 transmit interrupt request
UART0 receive interrupt or ACK interrupt request
UART1 transmit interrupt request
UART1 receive interrupt or ACK interrupt request
UART2 transmit interrupt request
UART2 receive interrupt or ACK interrupt request
UART3 transmit interrupt request
UART3 receive interrupt or ACK interrupt request
UART4 transmit interrupt request
UART4 receive interrupt or ACK interrupt request
A/D0 interrupt request
Intelligent I/O interrupt 0
request
Intelligent I/O interrupt 1
request
Intelligent I/O interrupt 2
request
Intelligent I/O interrupt 3
request
Intelligent I/O interrupt 4
request
Intelligent I/O interrupt 5
request
Intelligent I/O interrupt 6
request
(4)
(5)
(6)
DMA0
Falling edge of INT1
Both edges of INT1
Intelligent I/O interrupt 7
request
Intelligent I/O interrupt 8
request
Intelligent I/O interrupt 9
request
Intelligent I/O interrupt 10
request
Intelligent I/O interrupt 11
request
Intelligent I/O interrupt 0
request
Intelligent I/O interrupt 1
request
(7)
(8)
(9)
(4)
(5)
DMA1
DMA Request Source
(3)
(3)
(3)
(3)
(3)
2
C mode) and the IICM2 bit to 0 (NACK/ACK interrupt).
Falling edge of INT2
Both edges of INT2
Intelligent I/O interrupt 2
request
Intelligent I/O interrupt 3
request
Intelligent I/O interrupt 4
request
Intelligent I/O interrupt 5
request
Intelligent I/O interrupt 6
request
Intelligent I/O interrupt 7
request
Intelligent I/O interrupt 8
request
(6)
DMA2
Falling edge of INT3
Both edges of INT3
Intelligent I/O interrupt 9
request
Intelligent I/O interrupt 10
request
Intelligent I/O interrupt 11
request
Intelligent I/O interrupt 0
request
Intelligent I/O interrupt 1
request
Intelligent I/O interrupt 2
request
Intelligent I/O interrupt 3
request
(7)
(8)
(9)
(4)
(5)
DMA3
13. DMAC
(1)
(1)
(Note 2)
(Note 2)