M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 43

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 19 of 587
1.5
Table 1.15
I: Input
Power supply
Analog power
supply input
Reset input
CNVSS
External data
bus width
select input
Bus control
Pins
Type
Pin Functions
O: Output
Pin Functions (100-Pin and 144-Pin Packages) (1/4)
VCC1,VCC2
VSS
AVCC
AVSS
RESET
CNVSS
BYTE
D0 to D7
D8 to D15
A0 to A22
A23
A0/D0 to
A7/D7
A8/D8 to
A15/D15
CS0 to CS3
WRL/WR
WRH/BHE
RD
ALE
HOLD
HLDA
RDY
Symbol
I/O: Input and output
Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
−
−
I
I
I
I
I
Voltage
Supply
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
−
Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin.
The input condition of VCC1 ≥ VCC2 must be met.
Power supply input pins to the A/D converter and D/A converter.
Connect the AVCC pin to VCC1, and the AVSS pin to VSS.
The MCU is placed in the reset state while applying an “L” signal to
the RESET pin.
This pin switches processor mode. Apply an “L” to the CNVSS pin
to start up in single-chip mode, or an “H” to start up in
microprocessor mode (mask ROM, flash memory version) and boot
mode (flash memory version).
This pin switches a data bus width in external memory space 3. A
data bus is 16 bits wide when the BYTE pin is held “L” and 8 bits
wide when it is held “H”. Fix to either “L” or “H”.
Apply an “L” to the BYTE pin in single-chip mode.
Data (D0 to D7) input/output pins while accessing an external
memory space with separate bus.
Data (D8 to D15) input/output pins while accessing an external
memory space with 16-bit separate bus.
Address bits (A0 to A22) output pins.
Inverted address bit (A23) output pin.
Data (D0 to D7) input/output and 8 low-order address bits (A0 to
A7) output are performed by time-sharing these pins while
accessing an external memory space with multiplexed bus.
Data (D8 to D15) input/output and 8 middle-order address bits (A8
to A15) output are performed by time-sharing these pins while
accessing an external memory space with 16-bit multiplexed bus.
Chip-select signal output pins used to specify external devices.
WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH
can be switched with WR and BHE by a program.
• WRL, WRH and RD are selected:
• WR, BHE and RD are selected:
ALE signal is used for the external devices to latch address signals
when the multiplexed bus is selected.
The MCU is placed in a hold state while an “L” signal is applied to
the HOLD pin.
The HLDA pin outputs an “L” while the MCU is placed in a hold
state.
Bus is placed in a wait state while an “L” signal is applied to the
RDY pin.
If external data bus is 16 bits wide, data is written to an even
address in external memory space while an “L” is output from the
WRL pin. Data is written to an odd address while an “L” is output
from the WRH pin. Data is read while an “L” is output from the
RD pin.
Data is written while an “L” is output from the WR pin. Data is
read while an “L” is output from the RD pin. Data in odd address
is accessed while an “L” is output from the BHE pin. Select WR,
BHE and RD when an external data bus is 8 bits wide.
Description
1. Overview