M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 105

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 81 of 587
Figure 9.1
Stop mode
Stop mode
VC27: bit in the VCR2 register
CM02, CM04, CM05, and CM07: bits in the CM0 register
CM10 and CM17: bits in the CM1 register
CM21: bit in the CM2 regsiter
PM21, PM22, PM24, PM26, and PM27: bits in the PM2 register
CST: bit in the TCSPR register
CPSR: bit in the CPSRF register
NOTES:
Main clock
PLL frequency synthesizer
Interrupt priority level
Oscillation stop detection circuit
Clock stop signal
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. Bits MCD4 to MCD0 in the MCD register select the dividing ratio (divide-by-m mode: m = 1, 2, 3, 4, 6, 8, 10, 12, 14, 16).
3. To use the XIN clock as the CAN clock, set the PM24 bit to 1 when accessing the CAN module.
Main clock
CM05
CM04
Vdet4 detection
in wait mode
decision output
interrupt signal
RESET
Main clock oscillation circuit
NMI
Sub clock oscillation circuit
PM26
XCIN
XIN
Clock Generation Circuit
charge and discharge
Clock edge detect/
PM26
PM27
CM21
circuit control
XCOUT
XOUT
frequency counter
Programmable
Logic 1 write signal
Reference
PM22
counter
WAIT instruction
to CM10 bit
fC
PM21
fXIND
discharge circuit
comparator
Charge and
Phase
PLL frequency
Main clock
S
R Q
synthesizer
oscillator
On-chip
Clock stop signal
CM10
Enable oscillation
S Q
R
fCAN
in wait mode
Stop mode
VC27
fPLL
fROC
CM02
0
1
CM17
Loop
filter
Watchdog timer reset
CM05
CM21
Stop mode
Hardware reset 2
0
1
CM21
Oscillation stop detection
Software reset
interrupt request signal
interrupt request signal
generation circuit
interrupt request
Clock stop signal
fXIND
controlled
fROC
oscillator
Watchdog timer
Vdet4 detection
Voltage
(VCO)
in wait mode
Peripheral function
clock source: fPFC
PM27 and PM26
Clock stop signal in wait mode
00
01
10
CPSR=1
1/8
CST
1/4
1/32
VCO clock (fVCO)
Reset the divider
1/2n
MCD register
(divide-by-m)
1/2
1/3
Divider
fC32
fAD
f1
f8
f32
Reset the
divider (divide-
by-8 mode)
f2n
PLC12: bit in the PLC1 register
(2)
(1)
Oscillation stop detection
interrupt request
(non-maskable interrupt requst)
CM21
PLC12
0
1
CM07 PM24
9. Clock Generation Circuits
1
0
PLL clock (fPLL)
(3)
(bus clock)
CPU clock
fCPU