M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 117

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 93 of 587
Figure 9.12
9.1.4
Table 9.3
Multiplication
PRCR register: PRC0 bit = 1
CM2 register: CM21 bit = 0
CM0 register: CM07 bit = 0
PLC0 register: PLC07 bit = 1
CM1 register : CM17 bit = 1
PRC0 bit = 0
The PLL frequency synthesizer generates the PLL clock by multiplying the main clock. The PLL clock can be
used as the clock source for the CPU clock and peripheral function clocks.
The PLL frequency synthesizer is stopped after reset. When the PLC07 bit in the PLC0 register is set to 1 (PLL
runs), the PLL frequency synthesizer starts operating. Waiting time, tsu(PLL), is required before the PLL clock
is stabilized.
The PLL clock is the VCO clock divided by either 2 or 3. When the PLL clock is used as the clock source for
the CPU clock or peripheral function clocks, set each bit as shown in Table 9.3. Figure 9.12 shows the
procedure to use the PLL clock as the CPU clock source.
Prior to entering wait mode or stop mode, set the CM17 bit in the CM1 register to 0 (main clock as CPU clock
source) and then the PLC07 bit to 0 (PLL stops).
factor
8/3
2
3
4
PLL Clock
Set registers PLC0 and PLC1
Bit Settings to Use PLL Clock as CPU Clock Source
Procedure to Use PLL Clock as CPU Clock Source
Wait for tsu(PLL)
PLC02 bit
Start
0
1
End
PLC0 Register
PLC01 bit
1
0
Enable writing to registers associated with clocks
Select the main clock as the CPU clock source
(Set after a main clock oscillation stabilizes)
Select the multiplication factor for the PLL clock
(Set registers PLC0 and PLC1 simultaneously in 16-bit units)
PLC1
00000010 01010011b
00000010 01010100b
00000110 01010011b
00000110 01010100b
PLL runs
Wait for PLL frequency synthesizer to stabilize
Select the PLL clock as the clock source for the CPU clock
and peripheral function clock
Disable writing to registers associated with clocks
PLC00 bit
1
0
PLC0
PLC1 Register
PLC12 bit
Multiplication factor for PLL clock
×
×
×
×
1
0
1
0
6/2 = 3
8/2 = 4
6/3 = 2
8/3 = 2.66
9. Clock Generation Circuits
fPLL = 8/3 × fXIN
fPLL = 2 × fXIN
fPLL = 3 × fXIN
fPLL = 4 × fXIN
PLL Clock