M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 420

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 396 of 587
Figure 22.59
Group 2 IEBus Control Register
Group 2 IEBus Address Register
b15
b7 b6 b5 b4
NOTES:
1. Change the IEB bit setting while fBT2 is stopped.
2. When the IEB bit is set to 0, maintain the value for one or more fBT2 clock cycles. Set bits BCK1 and BCK0 in the G2BCR0
register to 00b (clock stop) when the IEB bit is set back to 1.
b8 b7
b3
b2
IECR and IEAR Registers
b1
b0
b0
Bit Symbol
Address data
Address data
Unimplemented.
Write 0. Read as undefined value.
(b5-b3)
IEBBS
IETS
IEM
IEB
DF
Symbol
IECR
−
Symbol
IEAR
IEBus enable bit
IEBus transmit operation start
request bit
IEBus busy flag
Unimplemented.
Write 0. Read as undefined value.
Digital filter select bit
IEBus mode select bit
Bit Name
(1)
Address
0172h
Address
0171h - 0170h
22. Intelligent I/O (Group 2 Communication Function)
Function
0 : IEBus disabled
1 : IEBus enabled
0 : Transmit operation completed
1 : Transmit operation started
0 : Idle state
1 : Busy state (start condition detected)
0 : No digital filter
1 : Digital filter
0 : Mode 1
1 : Mode 2
(2)
Function
After Reset
00XX X000b
After Reset
Undefined
RW
RW
RW
RW
RW
RW
RW
RW
RO
−
−