M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 177

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 153 of 587
Figure 14.2
14.1.2
Memory-to-Memory Transfer, Immediate Transfer,
Calculation Transfer
Starting Address
DMACII Index
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The DMACII index is an 8- to 32-byte data table, which stores parameters for transfer mode, transfer counter,
source address (or immediate data), operation address as an address to be calculated, destination address, chain
transfer address, and end-of-transfer interrupt address.
The DMACII index must be located on the RAM area.
Figure 14.2 shows a configuration of the DMACII index. Table 14.2 lists an example configuration of the
DMACII index.
Details of the DMACII index are described below. Set these parameters in the specified order listed in Table
14.2, depending on DMACII transfer mode.
MOD is two-byte data and required to set transfer mode. Figure 14.3 shows a configuration for transfer mode.
COUNT is two-byte data and required to set the number of transfer.
SADR is two-byte data and required to set a source memory address or immediate data.
OADR is two-byte data and required to set a memory address to be calculated. Set this data only when using the
calculation transfer function.
DADR is two-byte data and required to set a destination memory address.
CADR is four-byte data and required to set the starting address of the DMACII index for the next transfer. Set
this data only when using the chain transfer function.
IADR is four-byte data and required to set a jump address for end-of-transfer interrupt processing. Set this data
only when using the end-of-transfer interrupt.
The abbreviations shown in parentheses( ) for each parameter are used in this section.
Transfer mode (MOD)
Transfer counter (COUNT)
Transfer source address (SADR)
Operation address (OADR)
Transfer destination address (DADR)
Chain transfer address (CADR)
End-of-transfer interrupt address (IADR)
NOTES:
Place the DMACII index in the RAM. Necessary data must be set top-aligned without any space. For example, if not using the
calculation transfer function, assign a transfer destination address to BASE+6.
The starting address of the DMACII index must be assigned to the interrupt vector of the peripheral function interrupt triggering
a DMACII request.
BASE+2
BASE+4
BASE+6
BASE+8
BASE+10
BASE+12
BASE+14
BASE+16
(BASE)
DMACII Index
1. This data is not needed unless using the calculation transfer function.
2. This data is not needed unless using the chain transfer function.
3. This data is not needed unless using the end-of-transfer interrupt.
DMACII Index
Transfer mode (MOD)
Transfer counter (COUNT)
Transfer source address (or immediate data) (SADR)
Operation address
Transfer destination address (DADR)
Chain Transfer Address (lower byte)
Chain Transfer Address (higher byte)
End-of-Transfer Interrupt Address (lower byte)
(IADR0)
End-of-Transfer Interrupt Address (higher byte)
(IADR1)
(1)
(OADR)
16 bits
(2)
(2)
(CADR0)
(CADR1)
(3)
(3)
BASE+2
BASE+4
BASE+6
BASE+8
BASE+10
BASE+28
BASE+30
Multiple Transfer
BASE
Transfer mode (MOD)
Transfer counter (COUNT)
Transfer source address (SADR1)
Transfer destination address (DADR1)
Transfer source address (SADR2)
Transfer destination address (DADR2)
Transfer source address (SADR7)
Transfer destination address (DADR7)
to
16 bits
14. DMACII