M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 167

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 143 of 587
Figure 13.4
b23
b15
DMAi Memory Address Reload Register
DMAi Transfer Count Register (i = 0 to 3)
b15
DMAi Transfer Count Reload Register (i = 0 to 3)
NOTES:
NOTES:
NOTES:
b16 b15
1. Use the LDC instruction to set registers DRA0 to DRA3.
2. To set the DRA2 register, write to the SVP register.
3. To set the DRA3 register, write to the VCT register.
1. Use the LDC instruction to set registers DRC0 and DRC1.
2. To set the DRC2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R2 register.
3. To set the DRC3 register, set the B flag to 1 and write to the R3 register.
1. When the DCTi register is set to 0000h, no data transfer occurs regardless of a DMA request generation.
2. Use the LDC instruction to set registers DCT0 and DCT1.
3. To set the DCT2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R0 register.
4. To set the DCT3 register, set the B flag to 1 and write to the R1 register.
b8 b7
b8 b7
b8 b7
DRA0 to DRA3 Registers, DCT0 to DCT3 Registers, DRC0 to DRC3 Registers
b0
b0
b0
Set an incremented source address or incremented destination
address
Set the number of transfers
Set the number of transfers
Symbol
DRA0
DRA1
DRA2 (SVP)
DRA3 (VCT)
Symbol
Symbol
DCT0
DCT1
DCT2 (bank1:R0)
DCT3 (bank1:R1)
DRC0
DRC1
DRC2 (bank1:R2)
DRC3 (bank1:R3)
(2)
(2)
(1)
(1)
(2)
(3)
(3)
(4)
(2)
(3)
Function
Function
Function
(1)
Address
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
Address
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
Address
(CPU internal register)
(CPU internal register)
(CPU internal register)
(CPU internal register)
(i = 0 to 3)
000000h to FFFFFFh
0000h to FFFFh
0000h to FFFFh
Setting Range
Setting Range
Setting Range
(16 Mbytes)
After Reset
After Reset
XXXXXXh
XXXXXXh
XXXXXXh
XXXXXXh
After Reset
XXXXh
XXXXh
0000h
0000h
XXXXh
XXXXh
0000h
0000h
(1)
RW
RW
RW
RW
RW
RW
13. DMAC