M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 173

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 149 of 587
13.2
13.3
Table 13.3
Table 13.4
i=0 to 3, p=0 and 1
8-bit transfer
(BWi bit in the DMDp
register = 0)
16-bit transfer
(BWi bit = 1)
The DMA transfer time can be calculated as follows. (in terms of bus clock)
Table 13.3 lists the number of the source read cycle and destination write cycle. Table 13.4 lists coefficient j, k (the
number of bus clock).
Transfer time = source read bus cycle × j + destination write bus cycle × k
When multiple DMA requests are generated in the same sampling period (between a falling edge of the BCLK and
the next falling edge), the corresponding DRQ bits in the DMiSL register (i = 0 to 3) are set to 1 (requested)
simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3. Leave the following period
between each DMA transfer request generation on the same channel.
DMA request interval ≥ (number of channels set for DMA transfer - 1) × 5 BCLK cycles
Described in the following is the operation when DMA0 and DMA1 requests are generated in the same sampling
period. Figure 13.9 shows an example of DMA transfers triggered by the INT interrupts.
In Figure 13.9, DMA0 and DMA1 requests are generated simultaneously. A DMA0 request having higher priority
is acknowledged first to start a transfer. After one DMA0 transfer is completed, the DMAC returns ownership of
the bus to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1
transfer is completed, bus ownership is again returned to the CPU.
DMA requests cannot be counted up since each channel has one DRQ bit. Even if multiple DMA1 requests are
generated before receiving bus ownership as shown in Figure 13.9, the DRQ bit is set to 0 as soon as bus ownership
is acquired. Bus ownership is returned to the CPU after one transfer is completed.
with no wait state
Internal ROM or
internal RAM
Transfer Unit
DMA Transfer Time
Channel Priority and DMA Transfer Timing
k=1
j=1
Source Read Cycle and Destination Write Cycle
Coefficient j, k
Internal Space
16 bits
8 bits
16 bits
8 bits
Internal ROM or
with wait state
Bus Width
internal RAM
k=2
j=2
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Address
Access
SFR area
k=2
j=2
Read Cycle
Accessing Internal Space
j and k BCLK cycles shown in Table 8.6 (j, k = 2 to 9).
Add one cycle to j or k cycles when inserting a recovery
cycle
1
1
−
−
1
2
−
−
Write Cycle
1
1
1
−
−
2
−
−
External Space
Read Cycle
Accessing External Space
1
1
1
1
1
2
2
2
Write Cycle
13. DMAC
1
1
1
1
1
2
2
2