M3087BFLBGP#U5 Renesas Electronics America, M3087BFLBGP#U5 Datasheet - Page 278

• Manufacturer Part Number: M3087BFLBGP#U5
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLBGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 254 of 587
17.1.4
Table 17.14
NOTES:
Data format
Baud rate
Transmit/receive control
Transmit and receive
start condition
Interrupt request
generation timing
Error detection
Selectable function
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the
3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC
Full-duplex clock synchronous serial communications are allowed in this mode. SS function is used for transmit
and receive control. The input signal to the SSi pin (i = 0 to 4) determines whether the transmit and receive
operation is enabled or disabled. When it is disabled, the output pin is placed in a high-impedance state. Table
17.14 lists specifications of special mode 2. Table 17.15 lists pin settings. Figure 17.27 shows register settings.
UiC0 register is set to 0, and that an “L” signal is applied when the CKPOL bit is set to 1.
register remains unchanged as 0 (interrupt not requested).
Special Mode 2
Item
Special Mode 2 Specifications
Data length: 8 bits long
• The CKDiR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock):
• The CKDIR bit to 1 (external clock): input from the CLKi pin
• SS function
Internal clock is selected (master mode):
External clock is selected (slave mode)
If transmit-only operation is performed, the RE bit setting is not required in both cases.
Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):
Receive interrupt:
• Overrun error
• Mode error
• CLK polarity
• LSB first or MSB first
• Serial data logic inverse
• TXD and RXD I/O polarity Inverse
• Clock phase
Output pin is placed in a high-impedance state to avoid data conflict between a
master and other masters, or a slave and other slaves.
• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
• The TI bit in the UiC1 register is 0 (data in the UiTB register)
• Set the RE bit in the UiC1 register to 1 (receive operation enabled)
• “H” signal is applied to the SSi pin when the SS function is used
• Set the TE bit to 1
• The TI bit is 0
• Set the RE bit to 1
• “L” signal is applied to the SSi pin
• The UiIRS bit is set to 0 (no data in the UiTB register):
• The UiIRS bit is set to 1 (transmit operation completed):
• When data is transferred from the UARTi receive shift register to the UiRB register
Overrun error occurs when the 7th bit of the next data is received before reading the
UiRB register
Mode error occurs when an “L” signal is applied to the SSi pin in master mode
Transmit data output timing and receive data input timing can be selected
Data is transmitted or received from either bit 0 or bit 7
Transmit and receive data are logically inverted
The level output from the TXD pin and the level applied to the RXD pin are inverted.
One of four combinations of serial clock polarity and phase can be selected
fj / (2 (m + 1))
when data is transferred from the UiTB register to the UARTi transmit shift register
(transmit operation started)
when data transmit operation from the UARTi transmit shift register is completed
(receive operation completed)
fj = f1, f8, f2n
(3)
(1)
m: setting value of the UiBRG register (00h to FFh)
Specification
(2)
:
17. Serial Interfaces (UART0 to UART4)